Inventor
Peter Thomas Freiburger
Inventor
Rochester, MN, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores67%
H03KPulse technique21%
G06FElectric digital data processing9%
G01RMeasuring electric variables3%
PatentTitleYear
10,916,323Memory interface latch with integrated write-through and fence functions202110,381,098Memory interface latch with integrated write-through and fence functions201910,229,748Memory interface latch with integrated write-through function20199,087,563'SRAM local evaluation and write logic for column selection'20159,058,866'SRAM local evaluation logic for column selection'20158,488,368'Method for selectable guaranteed write-through with early read suppression'20138,427,894'Implementing single bit redundancy for dynamic SRAM circuit with any bit decode'20138,107,309'Bias temperature instability-influenced storage cell'20127,925,950'Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic'20117,835,176'Implementing enhanced dual mode SRAM performance screen ring oscillator'20107,724,586'Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage'20107,684,263'Method and circuit for implementing enhanced SRAM write and read performance ring oscillator'20107,681,095'Methods and apparatus for testing integrated circuits'20107,443,744'Method for reducing wiring and required number of redundant elements'20087,418,637'Methods and apparatus for testing integrated circuits'20087,161,390'Dynamic latching logic structure with static interfaces for implementing improved data setup time'20077,035,127'Method and sum addressed cell encoder for enhanced compare and search timing for CAM compare'20067,015,600'Pulse generator circuit and semiconductor device including same'20066,901,003'Lower power and reduced device split local and continuous bitline for domino read SRAMs'20056,741,493'Split local and continuous bitline requiring fewer wires'20046,657,886'Split local and continuous bitline for fast domino read SRAM'20036,538,522'Method and ring oscillator for evaluating dynamic circuits'20036,272,654'Fast scannable output latch with domino logic input'20016,247,166'Method and apparatus for assembling array and datapath macros'20016,172,531'Low power wordline decoder circuit with minimized hold time'20015,991,208'Write multiplexer apparatus and method for multiple write port programmable memory'19995,991,224'Global wire management apparatus and method for a multiple-port random access memory'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2021Patents assigned to IBM (27)· patent assignee history
1999–2021Based in Rochester, MN, US· patent location history
2012–2015Patents assigned to FREIBURGER PETER T (5)· patent assignee history
2013–2015Patents assigned to HEBIG TRAVIS R (3)· patent assignee history
2013Patents assigned to CHRISTENSEN TODD A (2)· patent assignee history
2013Patents assigned to BEHRENDS DERICK G (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 27 | 1999–2021 |
| FREIBURGER PETER Tself | 5 | 2012–2015 |
| HEBIG TRAVIS R | 3 | 2013–2015 |
| CHRISTENSEN TODD A | 2 | 2013 |
| BEHRENDS DERICK G | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Rochester, Minnesota, US | 27 | 1999–2021 |