Inventor
Shanghui Larry Tu
Inventor
Phoenix, AZ, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices50%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%
H01LSemiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
PatentTitleYear
10,790,389Source contact formation of MOSFET with gate shield buffer for pitch reduction202010,546,804Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact202010,446,687Integrated circuit connection arrangement for minimizing crosstalk201910,424,666Leadframe and integrated circuit connection arrangement201910,424,661Avalanche robust LDMOS201910,249,759Connection arrangements for integrated lateral diffusion field effect transistors201910,192,989Integrated circuit connection arrangement for minimizing crosstalk201910,083,897Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact20189,923,059'Connection arrangements for integrated lateral diffusion field effect transistors'20188,304,326'Edge seal for a semiconductor device and method therefor'20128,168,466'Schottky diode and method therefor'20128,049,309'Edge seal for a semiconductor device'20117,943,466'Method of forming a semiconductor device having sub-surface trench charge compensation regions'20117,875,950'Schottky diode structure with multi-portioned guard ring and method of manufacture'20117,799,640'Method of forming a semiconductor device having trench charge compensation regions'20107,682,955'Method for forming deep well of power device'20107,679,146'Semiconductor device having sub-surface trench charge compensation regions'20107,632,760'Semiconductor device having field stabilization film and method'20097,615,469'Edge seal for a semiconductor device and method therefor'20097,411,266'Semiconductor device having trench charge compensation regions and method'20087,381,603'Semiconductor structure with improved on resistance and breakdown voltage performance'20087,276,766'Semiconductor structure with improved on resistance and breakdown voltage performance'20077,126,166'High voltage lateral FET structure with improved on resistance performance'20066,982,461'Lateral FET structure with improved blocking voltage and on resistance performance and method'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2012Patents assigned to SEMICONDUCTOR COMPONENTS IND (13)· patent assignee history
2006–2012Based in Phoenix, AZ, US· patent location history
2010Based in Tainan, TW· patent location history
2012Patents assigned to TU SHANGHUI L (2)· patent assignee history
2012Patents assigned to GRIVNA GORDON M (1)· patent assignee history
2012Patents assigned to HOSSAIN ZIA (1)· patent assignee history
2018–2020Patents assigned to SILANNA ASIA PTE LTD (9)· patent assignee history
2018–2020Based in San Diego, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SEMICONDUCTOR COMPONENTS IND | 13 | 2006–2012 |
| SILANNA ASIA PTE LTD | 9 | 2018–2020 |
| TU SHANGHUI Lself | 2 | 2012 |
| GRIVNA GORDON M | 1 | 2012 |
| HOSSAIN ZIA | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Phoenix, AZ, US | 14 | 2006–2012 |
| San Diego, California, US | 9 | 2018–2020 |
| Tainan, TW | 1 | 2010 |