Inventor
Shinye Shiu
Inventor
Los Altos, CA, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing38%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use28%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications16%
G11CStatic stores8%
G09GArrangements or circuits for control of indicating devices using static means to present variable information5%
H01LSemiconductor devices2%
H03KPulse technique2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
10,802,968Processor to memory with coherency bypass202010,607,977Integrated DRAM with low-voltage swing I/O202010,310,586Memory power savings in idle display case201910,203,901Transparent hardware-assisted memory decompression201910,089,239Memory system architecture20189,892,054'Method and apparatus for monitoring system performance and dynamically updating memory sub-system settings using software to optimize performance and power consumption'20189,864,541'Transparent hardware-assisted memory decompression'20189,785,571'Methods and systems for memory de-duplication'20179,740,631'Hardware-assisted memory compression management using page filter and system MMU'20179,465,740'Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers'20169,400,544'Advanced fine-grained cache power management'20169,396,122'Cache allocation scheme optimized for browsing applications'20169,311,251'System cache with sticky allocation'20169,280,471'Mechanism for sharing private caches in a SoC'20169,261,939'Memory power savings in idle display case'20169,218,286'System cache with partial write valid states'20159,218,040'System cache with coarse grain power management'20159,201,796'System cache with speculative read engine'20159,158,685'System cache with cache hint control'20159,135,177'Scheme to escalate requests with address conflicts'20159,043,570'System cache with quota-based control'20158,984,227'Advanced coarse-grained cache power management'20158,977,817'System cache with fine grain power management'20158,912,853'Dynamic level shifter circuit and ring oscillator using the same'20148,886,886'System cache with sticky removal engine'20148,559,247'Dynamic level shifter for interfacing signals referenced to different power supply domains'20138,493,811'Memory having asynchronous read with fast read output'20138,134,874'Dynamic leakage control for memory arrays'20128,036,061'Integrated circuit with multiported memory supercell and data path switching circuitry'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2020Patents assigned to APPLE INC (22)· patent assignee history
2011–2018Based in Mountain View, CA, US· patent location history
2012–2016Patents assigned to SHIU SHINYE (7)· patent assignee history
2014–2020Based in Los Altos, CA, US· patent location history
2015–2016Patents assigned to BISWAS SUKALPA (3)· patent assignee history
2017–2018Patents assigned to GOOGLE INC (5)· patent assignee history
2018–2020Patents assigned to GOOGLE LLC (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLE INC | 22 | 2011–2020 |
| SHIU SHINYEself | 7 | 2012–2016 |
| GOOGLE INC | 5 | 2017–2018 |
| GOOGLE LLC | 5 | 2018–2020 |
| BISWAS SUKALPA | 3 | 2015–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos, California, US | 21 | 2014–2020 |
| Mountain View, California, US | 8 | 2011–2018 |