Inventor
CHI-WEN LIU
Inventor
TW
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
H01LSemiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
B82YSpecific uses or applications of nanostructures4%
H10BElectronic memory devices2%
PatentTitleYear
12,563,821Semiconductor device and fabricating method thereof202612,453,116Transistors with stacked channels and the methods of forming the same202512,237,380Semiconductor device and method of forming the same202512,218,203Integrated circuit structure and method with solid phase diffusion202512,068,383Wrap around silicide for FinFETs202412,040,3793D capacitor and method of manufacturing same202412,034,077Method of forming source/drain regions with expanded widths202412,027,522Systems and methods for fabricating FinFETs with different threshold voltages202411,894,448Structure and method for vertical tunneling field effect transistor with leveled source and drain202411,855,219Passivated and faceted for fin field effect transistor202311,837,6463D capacitor and method of manufacturing same202311,798,989Strained nanowire CMOS device and method of forming202311,784,241Devices including gate spacer with gap or void and methods of forming the same202311,749,603Interconnection structure, fabricating method thereof, and semiconductor device using the same202311,749,720Integrated circuit structure and method with solid phase diffusion202311,749,724Semiconductor device and method of forming the same202311,688,787Semiconductor device having modified profile metal gate202311,682,625Interconnection structure, fabricating method thereof, and semiconductor device using the same202311,664,218Semiconductor device and method202311,652,141Strained nanowire CMOS device and method of forming202311,631,768Semiconductor device and method of manufacturing thereof202311,594,619Devices including gate spacer with gap or void and methods of forming the same202311,532,500FinFET structure with different fin heights and method for forming the same202211,437,479Wrap around silicide for FinFETs202211,404,376Interconnection structure, fabricating method thereof, and semiconductor device using the same202211,362,087Systems and methods for fabricating FinFETs with different threshold voltages202211,362,004FinFET devices and methods of forming202211,335,809Stacked Gate-All-Around FinFET and method forming the same202211,309,385Strained nanowire CMOS device and method of forming202211,211,498FinFETs with wrap-around silicide and method forming the same202111,205,594Fin spacer protected source and drain regions in FinFETs202111,158,743Passivated and faceted for fin field effect transistor2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (32)· patent assignee history
2021–2026Based in TW· patent location history
2023Patents assigned to UNIV NAT TAIWAN (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 32 | 2021–2026 |
| UNIV NAT TAIWAN | 2 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 32 | 2021–2026 |