Inventor
Kenneth J. Goodnow
Inventor
Essex Junction, VT, US
Overview
Patents· 104 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing39%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%
H03KPulse technique8%
G11CStatic stores5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G01RMeasuring electric variables3%
H01LSemiconductor devices3%
H10DInorganic electric semiconductor devices3%
H04BTransmission2%
H04LTransmission of digital information, e.g. telegraphic communication2%
PatentTitleYear
9,337,173'Three-dimensional inter-chip contact through vertical displacement MEMS'20169,301,424'Auto-compensating temperature valve controller for electro-rheological fluid micro-channel cooled integrated circuit'20169,264,150'Reactive metal optical security device and methods of fabrication and use'20169,257,366'Auto-compensating temperature valve controller for electro-rheological fluid micro-channel cooled integrated circuit'20169,230,940'Three-dimensional chip stack for self-powered integrated circuit'20169,123,492'Three-dimensional inter-chip contact through vertical displacement MEMS'20159,052,724'Electro-rheological micro-channel anisotropic cooled integrated circuits and methods thereof'20158,575,964'Inactivity triggered self clocking logic family'20138,549,335'Secondary power utilization during peak power times'20138,513,948'Microelectromechanical structure (MEMS) monitoring'20138,452,566'Warranty monitoring and enforcement for integrated circuit and related design structure'20138,436,638'Switch to perform non-destructive and secure disablement of IC functionality utilizing MEMS and method thereof'20138,407,633'Dynamically reconfigurable self-monitoring circuit'20138,347,019'Structure for hardware assisted bus state transition circuit using content addressable memories'20138,301,921'Secondary power utilization during peak power times'20128,291,357'On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations'20128,174,329'Power management architecture and method of modulating oscillator frequency based on voltage supply'20128,132,136'Dynamic critical path detector for digital logic circuit paths'20128,122,273'Structure and method to optimize computational efficiency in low-power environments'20128,122,165'On-demand power supply current modification system and method for an integrated circuit'20128,103,388'System for prediction and communication of environmentally induced power useage limitation'20128,055,925'Structure and method to optimize computational efficiency in low-power environments'20118,020,137'Structure for an on-demand power supply current modification system for an integrated circuit'20118,010,813'Structure for system for extending the useful life of another system'20117,949,978'Structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit'20117,941,772'Dynamic critical path detector for digital logic circuit paths'20117,937,560'Processor pipeline architecture logic state retention systems and methods'20117,913,193'Determining relative amount of usage of data retaining device based on potential of charge storing device'20117,903,493'Design structure for estimating and/or predicting power cycle length, method of estimating and/or predicting power cycle length and circuit thereof'20117,895,459'Structure for a system and method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly'20117,882,334'Processor pipeline architecture logic state retention systems and methods'20117,869,298'Determining relative amount of usage of data retaining device based on potential of charge storing device'20117,865,789'System and method for system-on-chip interconnect verification'20117,849,426'Mechanism for detection and compensation of NBTI induced threshold degradation'20107,831,935'Method and architecture for power management of an electronic device'20107,823,017'Structure for task based debugger (transaction-event-job-trigger)'20107,791,968'Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator'20107,793,251'Method for increasing the manufacturing yield of programmable logic devices'20107,793,163'Method and system for extending the useful life of another system'20107,750,670'System and method for dynamically executing a function in a programmable logic array'20107,739,637'Partial good schema for integrated circuits having parallel execution units'20107,732,949'System for method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly'20107,715,995'Design structure for measurement of power consumption within an integrated circuit'20107,716,615'Redundant critical path circuits to meet performance requirement'20107,633,819'Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator'20097,594,140'Task based debugger (transaction-event-job-trigger)'20097,579,897'Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices'20097,545,165'System architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit'20097,519,941'Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry'20097,512,813'Method for system level protection of field programmable logic devices'20097,504,847'Mechanism for detection and compensation of NBTI induced threshold degradation'20097,489,163'FPGA powerup to known functional state'20097,460,422'Determining history state of data based on state of partially depleted silicon-on-insulator'20087,454,642'Method and architecture for power management of an electronic device'20087,437,620'Method and system for extending the useful life of another system'20087,417,453'System and method for dynamically executing a function in a programmable logic array'20087,397,718'Determining relative amount of usage of data retaining device based on potential of charge storing device'20087,353,486'Data processing in digital systems'20087,313,738'System and method for system-on-chip interconnect verification'20077,308,668'Apparatus and method for implementing an integrated circuit IP core library architecture'20077,307,467'Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices'20077,304,493'FPGA powerup to known functional state'20077,302,605'Method and structure for replacing faulty operating code contained in a ROM for a processor'20077,286,770'Fiber optic transmission lines on an SOC'20077,282,949'FPGA powerup to known functional state'20077,275,011'Method and apparatus for monitoring integrated circuit temperature through deterministic path delays'20077,249,279'Multiprocessor code fix using a local cache'20077,248,838'Wireless communication system within a system on a chip'20077,222,248'Method of switching voltage islands in integrated circuits when a grid voltage at a reference location is within a specified range'20077,139,881'Semiconductor device comprising a plurality of memory structures'20067,134,104'Method of selectively building redundant logic structures to improve fault tolerance'20067,129,821'Communication systems and methods using microelectronics power distribution network'20067,107,469'Power down processing islands'20067,103,320'Wireless communication system within a system on a chip'20067,085,993'System and method for correcting timing signals in integrated circuits'20067,065,733'Method for modifying the behavior of a state machine'20066,996,795'Data processing in digital systems'20066,954,085'System and method for dynamically executing a function in a programmable logic array'20056,825,711'Power reduction by stage in integrated circuit'20046,802,033'Low-power critical error rate communications controller'20046,658,634'Logic power optimization algorithm'20036,604,174'Performance based system and method for dynamic allocation of a unified multiport cache'20036,541,997'Clockless impedance controller'20036,532,520'Method and apparatus for allocating data and instructions within a shared cache'20036,397,170'Simulation based power optimization'20026,345,362'Managing Vt for reduced power using a status table'20026,317,840'Control of multiple equivalent functional units for power reduction'20016,275,968'Apparatus and method to reduce node toggling in semiconductor devices'20016,237,132'Toggle based application specific core methodology'20016,167,524'Apparatus and method for efficient battery utilization in portable personal computers'20006,141,351'Radio frequency bus for broadband microprocessor communications'20006,134,704'Integrated circuit macro apparatus'20006,107,841'Synchronous clock switching circuit for multiple asynchronous clock source'20006,097,243'Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode'20006,097,241'ASIC low power activity detector to change threshold voltage'20006,081,135'Device and method to reduce power consumption in integrated semiconductor devices'20006,026,471'Anticipating cache memory loader and method'20006,011,383'Low powering apparatus for automatic reduction of power in active and standby modes'20005,986,962'Internal shadow latch'19995,918,246'Apparatus and method for prefetching data based on information contained in a compiler generated program map'19995,902,044'Integrated hot spot detector for design, analysis, and control'19995,793,815'Calibrated multi-voltage level signal transmission system'19985,781,922'Page boundary caches'19985,710,892'System and method for asynchronous dual bus conversion using double state machines'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2016Patents assigned to IBM (103)· patent assignee history
1998–2016Based in Essex Junction, VT, US· patent location history
1998–2013Based in Essex, VT, US· patent location history
2000Based in South Burlington, VT, US· patent location history
2012–2016Patents assigned to GOODNOW KENNETH J (15)· patent assignee history
2012–2013Patents assigned to TWOMBLY PETER A (10)· patent assignee history
2012–2016Patents assigned to WOODRUFF CHARLES S (6)· patent assignee history
2012–2016Patents assigned to OGILVIE CLARENCE R (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 103 | 1998–2016 |
| GOODNOW KENNETH Jself | 15 | 2012–2016 |
| TWOMBLY PETER A | 10 | 2012–2013 |
| WOODRUFF CHARLES S | 6 | 2012–2016 |
| OGILVIE CLARENCE R | 5 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 82 | 1998–2016 |
| Essex, VT, US | 21 | 1998–2013 |
| South Burlington, VT, US | 1 | 2000 |