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Inventor

Andrew Michael Jones

Inventor
Bristol, GB

Overview

64→
Patents
1998–2016
Patent span
Physics
Primary field (CPC G)

Patents· 64 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing59%
H04LTransmission of digital information, e.g. telegraphic communication8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
G11CStatic stores2%
H01LSemiconductor devices2%
H04NPictorial communication, e.g. television2%
A01CPlanting1%
A61MDevices for introducing media into, or onto, the body1%
PatentTitleYear
9,367,517'Integrated circuit package with multiple dies and queue allocation'20169,311,246'Cache memory system'20169,208,096'Cache pre-fetching responsive to data availability'20159,105,316'Integrated circuit package with multiple dies and a multiplexed communications interface'20159,086,870'Circuit'20159,058,283'Cache arrangement'20159,026,774'IC with boot transaction translation and related methods'20158,996,815'Cache memory controller'20158,990,540'Integrated circuit system providing enhanced communications between integrated circuit dies and related methods'20158,930,637'Arrangement'20158,725,987'Cache memory system including selectively accessible pre-fetch memory for pre-fetch of variable size data'20148,653,638'Integrated circuit package with multiple dies and bundling of control signals'20148,629,544'Integrated circuit package with multiple dies and a multiplexed communications interface'20148,610,258'Integrated circuit package with multiple dies and sampled control signals'20138,521,937'Method and apparatus for interfacing multiple dies with mapping to modify source identity'20138,504,751'Integrated circuit package with multiple dies and interrupt processing'20138,468,381'Integrated circuit package with multiple dies and a synchronizer'20138,347,258'Method and apparatus for interfacing multiple dies with mapping for source identifier allocation'20138,260,994'Interface for prototyping integrated systems'20128,060,732'Multiple purpose integrated circuit'20118,051,237'Multiple purpose integrated circuit'20117,951,092'Guidewire loader apparatus and method'20117,860,252'Circuit security'20107,796,624'Systems and methods for providing single-packet and multi-packet transactions in an integrated circuit'20107,774,574'Prototyping integrated systems'2010D0566044'Connector'20087,346,072'Arbitration mechanism for packet transmission'2008D0561896'Guidewire loader apparatus for a medical device'20087,266,728'Circuit for monitoring information on an interconnect'20077,260,745'Detection of information on an interconnect'20077,228,389'System and method for maintaining cache coherency in a shared memory system'20077,197,600'Transferring data along with code for program overlays'20077,089,390'Apparatus and method to reduce memory footprints in processor architectures'20067,065,601'Interface for prototyping integrated systems'20067,047,245'Processing system'20067,000,078'System and method for maintaining cache coherency in a shared memory system'2006D0510739'Computer interface'20056,928,073'Integrated circuit implementing packet transmission'20056,826,191'Packets containing transaction attributes'20046,763,034'Connection ports for interconnecting modules in an integrated circuit'20046,757,759'Microcomputer chips with interconnected address and data paths'20046,697,931'System and method for communicating information to and from a single chip computer system through an external communication port with translation circuitry'20046,693,914'Arbitration mechanism for packet transmission'20046,658,514'Interrupt and control packets for a microcomputer'20036,598,177'Monitoring error conditions in an integrated circuit'20036,590,907'Integrated circuit with additional ports'20036,549,965'Microcomputer with interrupt packets'20036,526,501'Adapter for a microprocessor'20036,460,105'Method and system for transmitting interrupts from a peripheral device to another device in a computer system'20026,457,124'Microcomputer having address diversion means for remapping an on-chip device to an external port'20026,449,670'Microcomputer with bit packets for interrupts, control and memory access'20026,415,344'System and method for on-chip communication'20026,412,047'Coherency protocol'20026,401,191'System and method for remotely executing code'20026,397,325'Microcomputer with packet translation for event packets and memory access packets'20026,389,498'Microprocessor having addressable communication port'20026,356,960'Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port'20026,351,790'Cache coherency mechanism'20026,349,371'Circuit for storing information'20026,301,642'Shared memory bus arbitration system to improve access speed when accessing the same address set'20016,301,657'System and method for booting a computer'20016,298,394'System and method for capturing information on an interconnect in an integrated circuit'20016,240,540'Cyclic redundancy check in a computer system'20015,828,852'Method for operation of a bus system for highly flexible and quick data transmission between units connected to the bus system and configuration for carrying out the method'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2016Based in Bristol, GB· patent location history
2001–2008Patents assigned to SGS THOMSON MICROELECTRONICS (30)· patent assignee history
2001–2015Based in Redland, GB· patent location history
2006–2012Patents assigned to ST MICROELECTRONICS NV (3)· patent assignee history
2006–2007Based in Vancouver, CA· patent location history
2008–2011Based in San Jose, CA, US· patent location history
2008Based in Rosindale, MA, US· patent location history
2010–2016Patents assigned to ST MICROELECTRONICS RES & DEV (17)· patent assignee history
2011–2016Patents assigned to JONES ANDREW MICHAEL (18)· patent assignee history
2012–2016Patents assigned to RYAN STUART (18)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SGS THOMSON MICROELECTRONICS302001–2008
JONES ANDREW MICHAELself182011–2016
RYAN STUART182012–2016
ST MICROELECTRONICS RES & DEV172010–2016
ST MICROELECTRONICS NV32006–2012
Locations
LocationPatentsSpan
Bristol, GB451998–2016
Redland, GB132001–2015
San Jose, California, US22008–2011
Vancouver, CA22006–2007
Rosindale, Massachusetts, US12008