Inventor
Debra M. Bell
Inventor
Boise, ID, US
Overview
Patents· 60 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores46%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses16%
G06FElectric digital data processing15%
H01LSemiconductor devices5%
H03KPulse technique5%
H10BElectronic memory devices3%
H10DInorganic electric semiconductor devices3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
PatentTitleYear
11,088,153Integrated arrangements of pull-up transistors and pull-down transistors, and integrated static memory202111,087,829Phase charge sharing202111,062,755Memory with partial bank refresh202111,042,436Semiconductor device with modified access and associated methods and systems202111,024,367Memory with on-die data transfer202110,832,754Current monitor for a memory device202010,825,492Methods and apparatuses for command shifter reduction202010,803,969Memory authentication202010,803,926Memory with on-die data transfer202010,789,182System and method for individual addressing202010,762,946Memory with partial array refresh202010,748,600Phase charge sharing reduction202010,741,566Integrated arrangements of pull-up transistors and pull-down transistors, and integrated static memory202010,734,044Apparatuses and methods for latching data input bits202010,725,952Accessing status information202010,521,366System and method for individual addressing201910,468,421Memory cells and memory arrays201910,410,696Methods and apparatuses for command shifter reduction201910,388,334Scan chain operation in sensing circuitry201910,339,071System and method for individual addressing201910,303,632Accessing status information201910,268,602System and method for individual addressing201910,177,159Memory cells and memory arrays201910,134,461Apparatuses and methods for selective row refreshes201810,037,785Scan chain operation in sensing circuitry20189,892,770'Methods and apparatuses for command shifter reduction'20189,294,105'Delay line off-state control with power reduction'20169,286,967'Method for clock control in dynamic random access memory devices'20169,053,815'Circuit in dynamic random access memory devices'20159,047,978'Apparatuses and methods for selective row refreshes'20158,913,448'Apparatuses and methods for capturing data in a memory'20148,593,187'Delay line off-state control with power reduction'20138,237,474'Delay line off-state control with power reduction'20127,898,901'Method for controlling clock cycle time for reduced power consumption in a semiconductor memory device'20117,729,197'Memory device having a delay locked loop with frequency control'20107,583,115'Delay line off-state control with power reduction'20097,519,850'Method and unit for buffer control'20097,489,587'Semiconductor memory device capable of controlling clock cycle time for reduced power consumption'20097,423,462'Clock capture in clock synchronization circuitry'20087,423,463'Clock capture in clock synchronization circuitry'20087,414,444'Clock capture in clock synchronization circuitry'20087,378,891'Measure-controlled circuit with frequency control'20087,372,768'Memory with address management'20087,368,965'Clock capture in clock synchronization circuitry'20087,319,728'Delay locked loop with frequency control'20087,212,057'Measure-controlled circuit with frequency control'20077,155,630'Method and unit for selectively enabling an input buffer based on an indication of a clock transition'20067,123,541'Memory with address management'20067,095,261'Clock capture in clock synchronization circuitry'20067,072,433'Delay locked loop fine tune'20067,064,992'Method and apparatus for saving current in a memory device'20066,956,785'Method and apparatus for saving current in a memory device'20056,937,530'Delay locked loop “ACTIVE Command†reactor'20056,876,239'Delay locked loop “ACTIVE command†reactor'20056,834,023'Method and apparatus for saving current in a memory device'20046,801,070'Measure-controlled circuit with frequency control'20046,798,711'Memory with address management'20046,778,455'Method and apparatus for saving refresh current'20046,687,180'Driver control circuit'20046,545,928'Antifuse programming current limiter'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2021Patents assigned to MICRON TECHNOLOGY INC (57)· patent assignee history
2003–2021Based in Boise, ID, US· patent location history
2005Patents assigned to BELL DEBRA M (1)· patent assignee history
2012–2013Patents assigned to BELL DEBRA (2)· patent assignee history
2012–2013Patents assigned to GOMM TYLER J (2)· patent assignee history
2014–2020Based in Dallas, TX, US· patent location history
2015–2016Patents assigned to NANYA TECHNOLOGY CORP (2)· patent assignee history
2018–2020Based in Tokyo, JP· patent location history
2019–2020Based in Shinjuku-ku, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 57 | 2003–2021 |
| BELL DEBRAself | 2 | 2012–2013 |
| GOMM TYLER J | 2 | 2012–2013 |
| NANYA TECHNOLOGY CORP | 2 | 2015–2016 |
| BELL DEBRA Mself | 1 | 2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 41 | 2003–2021 |
| Dallas, Texas, US | 9 | 2014–2020 |
| Tokyo, JP | 6 | 2018–2020 |
| Shinjuku-ku, JP | 4 | 2019–2020 |