Inventor

Han-Chin Chiu

Inventor
Kaohsiung, TW

Overview

30→
Patents
2014–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 30 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices35%
H01LSemiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
B81BMicrostructural devices or systems, e.g. micromechanical devices1%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems1%
H01GCapacitors1%
PatentTitleYear
10,868,136Sidewall passivation for HEMT devices202010,847,316MIM device with laminated dielectric layers202010,522,647Sidewall passivation for HEMT devices201910,522,645Surface treatment and passivation for high electron mobility transistors201910,269,948High-electron-mobility transistor (HEMT) structure capable of protecting a III-V compound layer and manufacturing method thereof201910,170,579Surface treatment and passivation for high electron mobility transistors201910,164,038Method of implanting dopants into a group III-nitride structure and device formed201810,157,994High electron mobility transistor and method of forming the same201810,020,376Sidewall passivation for HEMT devices20189,978,844HEMT-compatible lateral rectifier structure20189,941,398High-electron-mobility transistor (HEMT) capable of protecting a III-V compound layer20189,899,493'High electron mobility transistor and method of forming the same'20189,876,093High electron mobility transistor and method of forming the same20189,847,401Semiconductor device and method of forming the same20179,685,525'Sidewall passivation for HEMT devices'20179,666,683'Surface treatment and passivation for high electron mobility transistors'20179,633,920'Low damage passivation layer for III-V based devices'20179,601,608'Structure for a gallium nitride (GaN) high electron mobility transistor'20179,564,330'Normally-off enhancement-mode MISFET'20179,525,054'High electron mobility transistor and method of forming the same'20169,449,867'VHF etch barrier for semiconductor integrated microsystem'20169,425,301'Sidewall passivation for HEMT devices'20169,373,689'High electron mobility transistor and method of forming the same'20169,236,464'Method of forming a high electron mobility transistor'20169,224,847'High electron mobility transistor and method of forming the same'20159,214,539'Gallium nitride transistor with a hybrid aluminum oxide layer as a gate dielectric'20159,130,026'Crystalline layer for passivation of III-N surface'20158,912,570'High electron mobility transistor and method of forming the same'20148,884,268'Diffusion barrier layer for group III nitride on silicon substrate'20148,803,158'High electron mobility transistor and method of forming the same'2014

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2014–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (6)· patent assignee history
2014Patents assigned to CHEN CHI-MING (2)· patent assignee history
2014Patents assigned to CHIU HAN-CHIN (2)· patent assignee history
2014Patents assigned to YU CHUNG-YI (2)· patent assignee history
2014–2020Based in Kaohsiung, TW· patent location history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (24)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG CO LTD242015–2020
TAIWAN SEMICONDUCTOR MFG62014–2016
CHEN CHI-MING22014
CHIU HAN-CHINself22014
YU CHUNG-YI22014
Locations
LocationPatentsSpan
Kaohsiung, TW302014–2020