Inventor
Pei-Chi Liu
Inventor
Portland, OR, US
Overview
Patents· 7 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices28%
H10DInorganic electric semiconductor devices24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
C23CCoating metallic material4%
G11CStatic stores4%
H01JElectric discharge tubes or discharge lamps4%
H03DDemodulation or transference of modulation from one carrier to another4%
H10BElectronic memory devices4%
PatentTitleYear
10,840,082Method to clean SnO202010,763,209MOS antifuse with void-accelerated breakdown202010,692,771Non-planar I/O and logic semiconductor devices having different workfunction on common substrate202010,340,220Compound lateral resistor structures for integrated circuitry201910,229,853Non-planar I/O and logic semiconductor devices having different workfunction on common substrate201910,192,969Transistor gate metal with laterally graduated work function201910,164,115Non-linear fin-based devices2018Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2018–2020Patents assigned to INTEL CORP (6)· patent assignee history
2018–2020Based in Portland, OR, US· patent location history
2019Based in Beaverton, OR, US· patent location history
2020Patents assigned to LAM RES CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 6 | 2018–2020 |
| LAM RES CORP | 1 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 6 | 2018–2020 |
| Beaverton, OR, US | 1 | 2019 |