Inventor
Michael I. Catherwood
Inventor
Georgetown, TX, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing83%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
G11CStatic stores6%
PatentTitleYear
10,983,931Central processing unit with enhanced instruction set202110,802,866Central processing unit with DSP engine and enhanced context switch capabilities202010,776,292Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit202010,248,521Run time ECC error injection scheme for hardware validation201910,120,815Configurable mailbox data buffer apparatus20189,858,083'Dual boot panel SWAP mechanism'20189,619,231'Programmable CPU register hardware context swap mechanism'20178,984,198'Data space arbiter'20158,856,406'Peripheral trigger generator'20148,688,964'Programmable exception processing latency'20148,645,729'External device power control during low power sleep mode without central processing unit intervention'20148,495,125'DSP engine with implicit mixed sign operands'20137,966,480'Register pointer trap to prevent errors due to an invalid pointer value in a register'20117,467,178'Dual mode arithmetic saturation processing'20087,243,372'Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection'20077,020,788'Reduced power option'20067,007,172'Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection'20066,976,158'Repeat instruction with interrupt'20056,952,711'Maximally negative signed fractional number multiplication'20056,934,728'Euclidean distance instructions'20056,728,856'Modified Harvard architecture processor having program memory space mapped to data memory space'20046,604,169'Modulo addressing based on absolute offset'20036,601,160'Dynamically reconfigurable data space'20035,890,191'Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory'19995,854,944'Method and apparatus for determining wait states on a per cycle basis in a data processing system'19985,680,632'Method for providing an extensible register in the first and second data processing systems'19975,598,569'Data processor having operating modes selected by at least one mask option bit and method therefor'19975,535,376'Data processor having a timer circuit for performing a buffered pulse width modulation function and method therefor'19965,457,802'Integrated circuit pin control apparatus and method thereof in a data processing system'19955,249,280'Microcomputer having a memory bank switching apparatus for accessing a selected memory bank in an external memory'19935,249,148'Method and apparatus for performing restricted modulo arithmetic'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–1999Patents assigned to MOTOROLA INC (8)· patent assignee history
1993–1999Based in Austin, TX, US· patent location history
2003–2021Patents assigned to MICROCHIP TECH INC (23)· patent assignee history
2003–2011Based in Pepperell, MA, US· patent location history
2006Based in MA, US· patent location history
2013–2015Patents assigned to CATHERWOOD MICHAEL I (3)· patent assignee history
2013–2021Based in Georgetown, TX, US· patent location history
2014Patents assigned to CATHERWOOD MICHAEL (2)· patent assignee history
2015Patents assigned to DESAI ASHISH (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICROCHIP TECH INC | 23 | 2003–2021 |
| MOTOROLA INC | 8 | 1993–1999 |
| CATHERWOOD MICHAEL Iself | 3 | 2013–2015 |
| CATHERWOOD MICHAELself | 2 | 2014 |
| DESAI ASHISH | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Georgetown, Texas, US | 12 | 2013–2021 |
| Pepperell, Massachusetts, US | 10 | 2003–2011 |
| Austin, Texas, US | 8 | 1993–1999 |
| Massachusetts, US | 1 | 2006 |