Inventor

Chia-Der Chang

Inventor
Hsinchu, TW

Overview

26→
Patents
2000–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 26 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1029%
H01LSemiconductor devices27%
H10DInorganic electric semiconductor devices27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10BElectronic memory devices2%
PatentTitleYear
10,763,280Hybrid FinFET structure202010,665,686Gate feature in finFET device202010,468,299Semiconductor device with an interconnect structure and method for forming the same201910,276,680Gate feature in FinFET device201910,115,596Method of fabricating a semiconductor device having a T-shape in the metal gate line-end201810,090,397Semiconductor device structure and method for forming the same201810,083,959Semiconductor device structure and method for forming the same201810,056,462Metal gate structure and manufacturing method thereof20189,941,152Mechanism for forming metal gate structure20189,923,056'Method of fabricating a MOSFET with an undoped channel'20189,911,650'Semiconductor device with an interconnect structure and method for forming the same'20189,780,213'Semiconductor device having a reversed T-shaped profile in the metal gate line-end'20179,748,232'Semiconductor device structure and method for forming the same'20179,577,026'MIM capacitor and method of forming the same'20179,570,584'Semiconductor structure and manufacturing method thereof'20179,564,510'Method of fabricating a MOSFET with an undoped channel'20179,564,332'Mechanism for forming metal gate structure'20179,496,367'Mechanism for forming metal gate structure'20169,478,626'Semiconductor device with an interconnect structure and method for forming the same'20169,331,178'Method for manufacturing non-planar field effect transistor having a semiconductor fin'20169,231,098'Mechanism for forming metal gate structure'20169,136,356'Non-planar field effect transistor having a semiconductor fin and method for manufacturing'20157,714,392'Method for forming an improved low power SRAM contact'20107,232,762'Method for forming an improved low power SRAM contact'20076,774,042'Planarization method for deep sub micron shallow trench isolation process'20046,143,579'Efficient method for monitoring gate oxide damage related to plasma etch chamber processing history'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000Patents assigned to TAIWAN SEMICONDUCTOR MFG LTD (1)· patent assignee history
2000Based in Chiai, TW· patent location history
2004–2010Patents assigned to TAIWAN SEMICONDUCTOR MFG (3)· patent assignee history
2004–2020Based in Hsinchu, TW· patent location history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (22)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG CO LTD222015–2020
TAIWAN SEMICONDUCTOR MFG32004–2010
TAIWAN SEMICONDUCTOR MFG LTD12000
Locations
LocationPatentsSpan
Hsinchu, TW252004–2020
Chiai, TW12000