Inventor
Jing Ling
Inventor
Fremont, CA, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Jprimary
H04JMultiplex communication30%
H04LTransmission of digital information, e.g. telegraphic communication25%
G06FElectric digital data processing23%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%
G06KGraphical data reading3%
G06VImage or video recognition or understanding3%
H04NPictorial communication, e.g. television3%
H04QSelecting3%
PatentTitleYear
11,036,634Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory202110,346,177Boot process with parallel memory initialization201910,198,354Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory201910,129,495Apparatus and method for generating local binary patterns (LBPS)20189,697,094'Dynamically changing lockstep configuration'20179,430,378'Differential delay compensation'20169,110,794'Differential delay compensation'20158,488,631'Differential delay compensation'20138,018,926'Differential delay compensation'20117,656,891'Method and apparatus enabling concurrent processing of contiguously and virtually concatenated payloads'20107,606,269'Method and apparatus for detecting and managing loss of alignment in a virtually concatenated group'20097,583,599'Transporting stream client signals via packet interface using GFP mapping'20097,564,777'Techniques for group alarm indication signal generation and clearing'20097,525,977'Control mechanism for mapping cells and packets'20097,508,830'Method and apparatus differential delay compensation processing of virtually concatenated data'20097,460,545'Enhanced SDRAM bandwidth usage and memory management for TDM traffic'20087,298,744'Method and apparatus for centralized processing of contiguously and virtually concatenated payloads'20077,295,564'Virtual output queue (VoQ) management method and apparatus'20077,154,853'Rate policing algorithm for packet flows'20067,065,628'Increasing memory access efficiency for packet applications'20067,061,867'Rate-based scheduling for packet applications'20066,944,728'Interleaving memory access'20056,892,284'Dynamic memory allocation for assigning partitions to a logical port from two groups of un-assigned partitions based on two threshold values'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2021Patents assigned to INTEL CORP (18)· patent assignee history
2005–2016Based in Fremont, CA, US· patent location history
2011–2013Patents assigned to CALDERON JUAN-CARLOS (2)· patent assignee history
2011–2013Patents assigned to LING JING (2)· patent assignee history
2011–2013Patents assigned to SUH SOOWAN (2)· patent assignee history
2013–2016Patents assigned to MICRON TECHNOLOGY INC (3)· patent assignee history
2017–2021Based in Milpitas, CA, US· patent location history
2018Based in San Diego, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 18 | 2005–2021 |
| MICRON TECHNOLOGY INC | 3 | 2013–2016 |
| CALDERON JUAN-CARLOS | 2 | 2011–2013 |
| LING JINGself | 2 | 2011–2013 |
| SUH SOOWAN | 2 | 2011–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 18 | 2005–2016 |
| Milpitas, California, US | 4 | 2017–2021 |
| San Diego, California, US | 1 | 2018 |