Inventor
Douglas C. Burger
Inventor
Bellevue, WA, US
Overview
Patents· 110 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing46%
H04LTransmission of digital information, e.g. telegraphic communication15%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes5%
G06NComputing arrangements based on specific computational models4%
H04WWireless communication networks3%
G11CStatic stores3%
G06TImage data processing or generation, in general2%
H03MCoding1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
PatentTitleYear
11,132,599Multi-function unit for programmable hardware nodes for neural network processing202111,126,433Block-based processor core composition register202111,099,906Handling tenant requests in a system that uses hardware acceleration components202111,048,517Decoupled processor instruction window and operand buffer202111,016,770Distinct system registers for logical processors202111,010,198Data processing system having a hardware acceleration plane and a software plane202110,977,104Partially reconfiguring acceleration components202110,963,379Coupling wide memory interface to wide write back paths202110,958,717Hardware implemented load balancing202110,936,316Dense read encoding for dataflow ISA202110,871,967Register read/write ordering202010,860,924Hardware node having a mixed-signal matrix vector unit202010,831,576Partially reconfiguring acceleration components202010,819,657Allocating acceleration component functionality for supporting services202010,776,115Debug support for block-based processor202010,768,936Block-based processor including topology and control registers to indicate resource sharing and size of logical processor202010,719,321Prefetching instruction blocks202010,705,892Automatically generating conversational services from a computing application202010,691,413Block floating point computations using reduced bit-width vectors202010,678,544Initiating instruction block execution using a register access instruction202010,606,651Free form expression accelerator with thread length-based thread assignment to clustered soft processor cores that share a functional circuit202010,606,672Micro-service framework derived from third-party apps202010,580,042Energy-efficient content serving202010,565,182Hardware LZMA compressor202010,540,588Deep neural network processing on hardware accelerators with stacked memory202010,528,119Dynamic power routing to hardware accelerators202010,511,478Changing between different roles at acceleration components201910,452,995Machine learning classification on hardware accelerators with stacked memory201910,452,399Broadcast channel architectures for block-based processors201910,445,097Multimodal targets in a block-based processor201910,425,472Hardware implemented load balancing201910,409,606Verifying branch targets201910,410,252Energy-efficient content serving201910,346,168Decoupled processor instruction window and operand buffer201910,333,781Changing between different roles at acceleration components201910,332,008Parallel decision tree processor architecture201910,324,926System and method for extracting and sharing application-related user data201910,311,483Energy-efficient content serving201910,296,392Implementing a multi-component service using plural hardware acceleration components201910,270,709Allocating acceleration component functionality for supporting services201910,257,342Validating stateful dynamic links in mobile applications201910,216,555Partially reconfiguring acceleration components201910,210,844Holographic near-eye display201910,198,263Write nullification201910,198,294Handling tenant requests in a system that uses hardware acceleration components201910,180,840Dynamic generation of null instructions201910,167,800Hardware node having a matrix vector unit with block-floating point processing201910,165,079Providing a persona-based application experience201810,108,817Privacy-preserving cookies for personalization without user tracking201810,095,519Instruction block address register201810,061,584Store nullification in the target field201810,031,756Multi-nullification201810,028,116De-siloing applications for personalization and task completion services201810,027,543Reconfiguring an acceleration component among interconnected acceleration components20189,983,938Locally restoring functionality at acceleration components20189,952,867Mapping instruction blocks based on block size20189,946,548Age-based management of instruction blocks in a processor instruction window20189,940,136Reuse of decoded instructions20189,916,116'Memory access and detecting memory failures using dynamically replicated memory based on a replication policy'20189,898,864'Shared tactile interaction and user safety in shared space multi-person immersive virtual reality'20189,847,980Protecting communications with hardware accelerators for increased workflow security20179,842,228'Local personal daemon'20179,819,542'Configuring acceleration components over a network'20179,792,252'Incorporating a spatial array into one or more programmable processor cores'20179,792,154'Data processing system having a hardware acceleration plane and a software plane'20179,781,128'Client-side integration framework of services'20179,760,401'Incentive-based app execution'20179,760,159'Dynamic power routing to hardware accelerators'20179,720,693'Bulk allocation of instruction blocks to a processor instruction window'20179,703,565'Combined branch target and predicate prediction'20179,696,802'Short range wireless powered ring for user interaction and sensing'20179,679,144'Protecting privacy in web-based immersive augmented reality'20179,652,327'Restoring service acceleration'20179,647,932'Network routing modifications for distribution of data'20179,606,836'Independently networkable hardware accelerators for increased workflow optimization'20179,590,655'Scalable high-bandwidth architecture for lossless compression'20179,575,539'Virtual machine power consumption measurement and management'20179,558,508'Energy-efficient mobile advertising'20179,560,055'Client-side integration framework of services'20179,547,496'Energy efficient multi-modal instruction issue'20179,507,066'Eyepiece for near eye display system'20169,473,944'Local personal daemon'20169,432,472'Accelerated training of personal daemons'20169,412,466'Approximate multi-level cell memory operations'20169,363,303'Network routing modifications for distribution of data'20169,326,675'Virtual vision correction for video display'20169,218,497'Incentive-based app execution'20159,116,728'Providing a persona-based application experience'20159,092,357'Remapping of inoperable memory blocks'20159,021,241'Combined branch target and predicate prediction for instruction blocks'20158,984,239'Hardware and operating system support for persistent memory on a memory bus'20158,943,043'Dynamic community-based cache for mobile search'20158,861,270'Approximate multi-level cell memory operations'20148,862,914'Virtual machine power consumption measurement and management'20148,839,358'Progressive authentication'20148,839,053'Error correcting pointers for non-volatile storage'20148,805,833'Enhancing personal data search with information from social networks'20148,768,847'Privacy enhancing personal data brokerage service'20148,719,537'Memory power tokens'20148,543,863'Efficiency of hardware memory access using dynamically replicated memory'20138,521,981'Memory power tokens'20138,447,911'Unordered load/store queue'20138,312,463'Resource management in computing scenarios'20128,255,742'Dynamically replicated memory'20128,180,997'Dynamically composing processor cores to form logical processors'20128,055,881'Computing nodes for executing groups of instructions'20116,557,080'Cache with dynamic control of sub-block fetching'20036,161,170'Multiple processor, distributed memory computer with out-of-order processing'20006,061,776'Multiple processor, distributed memory computer with out-of-order processing'20005,943,501'Multiple processor, distributed memory computer with out-of-order processing'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2003Based in Madison, WI, US· patent location history
2011–2013Based in Austin, TX, US· patent location history
2012–2017Patents assigned to MICROSOFT CORP (21)· patent assignee history
2012–2015Patents assigned to BURGER DOUGLAS C (8)· patent assignee history
2012–2018Based in Redmond, WA, US· patent location history
2013–2015Patents assigned to STRAUSS KARIN (5)· patent assignee history
2013–2014Based in Seattle, WA, US· patent location history
2014–2016Patents assigned to BURGER DOUGLAS CHRISTOPHER (5)· patent assignee history
2014–2021Based in Bellevue, WA, US· patent location history
2015–2021Patents assigned to MICROSOFT TECHNOLOGY LICENSING LLC (87)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICROSOFT TECHNOLOGY LICENSING LLC | 87 | 2015–2021 |
| MICROSOFT CORP | 21 | 2012–2017 |
| BURGER DOUGLAS Cself | 8 | 2012–2015 |
| BURGER DOUGLAS CHRISTOPHERself | 5 | 2014–2016 |
| STRAUSS KARIN | 5 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bellevue, Washington, US | 86 | 2014–2021 |
| Redmond, Washington, US | 15 | 2012–2018 |
| Madison, WI, US | 4 | 1999–2003 |
| Austin, Texas, US | 3 | 2011–2013 |
| Seattle, Washington, US | 2 | 2013–2014 |