Inventor
Richard L. Schober
Inventor
Cupertino, CA, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication47%
G06FElectric digital data processing40%
H03MCoding7%
G04FTime-interval measuring3%
H04BTransmission3%
PatentTitleYear
8,738,990'Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers'20148,726,124'Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers'20148,693,607'Self-timed timer'20147,512,695'Method and system to control the communication of data between a plurality of interconnect devices'20097,330,927'Apparatus and methodology for a pointer manager'20087,296,096'Method and system for configuring an interconnect device'20077,269,697'Apparatus and methodology for an input port scheduler'20077,237,016'Method and system to manage resource requests utilizing link-list queues within an arbiter associated with an interconnect device'20077,231,444'Method and management port for an indirect loop protocol associated with an interconnect device'20077,209,476'Method and apparatus for input/output port mirroring for networking system bring-up and debug'20077,150,021'Method and system to allocate resources within an interconnect device according to a resource allocation table'20067,124,241'Apparatus and methodology for a write hub that supports high speed and low speed data rates'20067,089,380'Method and system to compute a status for a circular queue within a memory device'20067,058,053'Method and system to process a multicast request pertaining to a packet received at an interconnect device'20067,043,569'Method and system for configuring an interconnect device'20067,016,996'Method and apparatus to detect a timeout condition for a data item within a process'20066,976,142'Method and system to provide simultaneous access by multiple pipelines to a table'20056,922,749'Apparatus and methodology for an input port of a switch that supports cut-through operation within the switch'20056,898,742'System and method for automatic deskew across a high speed, parallel interconnection'20056,839,794'Method and system to map a service level associated with a packet to one of a number of data streams at an interconnect device'20056,636,993'System and method for automatic deskew across a high speed, parallel interconnection'20036,493,320'Automatic initialization and tuning across a high speed, plesiochronous, parallel link'20026,003,064'System and method for controlling data transmission between network elements'19995,987,629'Interconnect fault detection and localization method and apparatus'19995,768,300'Interconnect fault detection and localization method and apparatus'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2005Patents assigned to FUJITSU LTD (6)· patent assignee history
1998–2014Based in Cupertino, CA, US· patent location history
2005Patents assigned to AGILENT TECHNOLOGIES INC (3)· patent assignee history
2006–2009Patents assigned to AVAGO TECHNOLOGIES GENERAL IP (7)· patent assignee history
2006–2007Patents assigned to PALAU ACQUISITION CORP DELAWAR (4)· patent assignee history
2014Patents assigned to CHA HUNGSE (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AVAGO TECHNOLOGIES GENERAL IP | 7 | 2006–2009 |
| FUJITSU LTD | 6 | 1998–2005 |
| PALAU ACQUISITION CORP DELAWAR | 4 | 2006–2007 |
| AGILENT TECHNOLOGIES INC | 3 | 2005 |
| CHA HUNGSE | 2 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 25 | 1998–2014 |