Inventor

CHERN-YOW HSU

Inventor
TW

Overview

53→
Patents
2021–2026
Patent span
Electricity
Primary field (CPC H)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary
H01LSemiconductor devices20%
H10NElectric solid-state devices not otherwise provided for19%
H10BElectronic memory devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10DInorganic electric semiconductor devices9%
G11CStatic stores3%
H10HInorganic light-emitting semiconductor devices having potential barriers2%
PatentTitleYear
12,538,711Method for forming a hard mask with a tapered profile202612,501,842Non-volatile memory device and manufacturing technology202512,501,625Hard mask for MTJ patterning202512,446,473Bottom electrode via and conductive barrier design to eliminate electrical short in memory devices202512,446,238Semiconductor device and method of forming the same202512,439,837Via structure and methods of forming the same202512,349,602Bottom electrode via and conductive barrier design to eliminate electrical short in memory devices202512,274,072Semiconductor memory device and method for fabricating the same202512,262,643Techniques for MRAM MTJ top electrode connection202512,245,528Memory device with composite spacer202512,165,996Bond pad with enhanced reliability202412,132,039Mask transfer method (and related apparatus) for a bumping process202412,133,470Semiconductor structure and method of forming the same202412,114,576Method for forming a hard mask with a tapered profile202412,087,826Method for forming a semiconductor structure202412,010,933Via structure and methods of forming the same202411,973,149Semiconductor device and method of forming the same202411,943,934Hard mask for MTJ patterning202411,910,620Magnetic tunnel junction device with residue-protection sidewall spacer and the method for forming a magnetic tunnel junction device with residue-protection sidewall spacer202411,856,750Semiconductor arrangement with capacitor202311,855,127Semiconductor structure and method for forming the same202311,844,285Magnetic tunnel junction memory cell with a buffer-layer and methods for forming the same202311,839,161Semiconductor structure202311,824,022Bond pad with enhanced reliability202311,805,660Semiconductor structure202311,800,822Memory device with composite spacer202311,785,861Semiconductor structure and method of manufacturing the same202311,765,980Method for forming a hard mask with a tapered profile202311,735,550Bump structure to prevent metal redeposit and to prevent bond pad consumption and corrosion202311,721,683Mask transfer method (and related apparatus) for a bumping process202311,683,990Techniques for MRAM MTJ top electrode connection202311,575,052Semiconductor device and method of forming the same202311,569,296Semiconductor structure202311,532,697Semiconductor structure and method for forming the same202211,515,473Semiconductor device including a magnetic tunneling junction (MTJ) device202211,508,782Hard mask for MTJ patterning202211,502,245Magnetoresistive random access memory cell and fabricating the same202211,495,743Non-volatile memory device and manufacturing technology202211,489,115VIA structure and methods of forming the same202211,476,337Method for forming a semiconductor structure202211,430,956RRAM cell structure with conductive etch-stop layer202211,367,832Method of making magnetoresistive random access memory device202211,362,265Semiconductor structure and method of manufacturing the same202211,342,378Magnetic tunnel junction device with residue-protection sidewall spacer and the method for forming a magnetic tunnel junction device with residue-protection sidewall spacer202211,302,663Film scheme for bumping202211,264,368Mask transfer method (and related apparatus) for a bumping process202211,258,007Reversed stack MTJ202211,244,914Bond pad with enhanced reliability202211,227,993Device with composite spacer and method for manufacturing the same202211,222,896Semiconductor arrangement with capacitor and method of fabricating the same202211,211,352Bump structure to prevent metal redeposit and to prevent bond pad consumption and corrosion202111,164,836Film scheme for bumping202111,158,797RRAM cell structure with conductive etch-stop layer2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (53)· patent assignee history
2021–2026Based in TW· patent location history
2024Patents assigned to TAIWAN SEMICONDUCTOR MFG CPMPANY LTD (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG CO LTD532021–2026
TAIWAN SEMICONDUCTOR MFG CPMPANY LTD12024
Locations
LocationPatentsSpan
TW532021–2026