Inventor
Howard S. Landis
Inventor
Underhill, VT, US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
G06FElectric digital data processing19%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10DInorganic electric semiconductor devices9%
Y02PClimate change mitigation technologies in the production or processing of goods8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
H10BElectronic memory devices4%
Y10TTechnical subjects covered by former us classification4%
B24BMachines, devices, or processes for grinding or polishing1%
PatentTitleYear
10,254,642Modifying design layer of integrated circuit (IC) using nested and non-nested fill objects20199,977,325Modifying design layer of integrated circuit (IC)20189,170,482'Trimming of dummy fill shapes holes to affect near-neighbor dummy fill shapes with built-in optical proximity corrections for semiconductor applications'20158,954,901'Parameter variation improvement'20158,839,177'Method and system allowing for semiconductor design rule optimization'20148,796,133'Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections'20148,739,078'Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications'20148,507,346'Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer'20138,423,945'Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes'20138,299,775'Current-aligned auto-generated non-equiaxial hole shape for wiring'20128,288,821'SOI (silicon on insulator) substrate improvements'20128,176,447'Formation of masks/reticles having dummy features'20128,138,607'Metal fill structures for reducing parasitic capacitance'20128,089,126'Method and structures for improving substrate loss and linearity in SOI substrates'20127,930,667'System and method of automated wire and via layout optimization description'20117,888,800'Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics'20117,886,240'Modifying layout of IC based on function of interconnect and related circuit and design structure'20117,858,269'Structure and method for sub-resolution dummy clear shapes for improved gate dimensional control'20107,861,208'Structure for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks'20107,791,166'Formation of dummy features and inductors in semiconductor fabrication'20107,739,648'Formation of masks/reticles having dummy features'20107,739,632'System and method of automated wire and via layout optimization description'20107,721,248'Circuit element function matching despite auto-generated dummy shapes'20107,709,967'Shapes-based migration of aluminum designs to copper damascene'20107,709,300'Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks'20107,703,053'Regional pattern density determination method and system'20107,689,961'Increased power line noise immunity in IC using capacitor structure in fill area'20107,573,130'Crack trapping and arrest in thin film structures'20097,537,941'Variable overlap of dummy shapes for improved rapid thermal anneal uniformity'20097,498,250'Shapes-based migration of aluminum designs to copper damascene'20097,491,578'Method of forming crack trapping and arrest in thin film structures'20097,479,701'Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics'20097,312,141'Shapes-based migration of aluminum designs to copper damascene'20077,269,818'Circuit element function matching despite auto-generated dummy shapes'20077,250,363'Aligned dummy metal fill and hole shapes'20077,015,582'Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics'20066,992,002'Shapes-based migration of aluminum designs to copper damascence'20066,743,710'Stacked fill structures for support of dielectric layers'20046,559,543'Stacked fill structures for support of dielectric layers'20036,528,883'Shapes-based migration of aluminum designs to copper damascene'20036,495,917'Method and structure of column interconnect'20026,444,581'AB etch endpoint by ABFILL compensation'20026,399,976'Shrink-wrap collar for DRAM deep trenches'20026,270,353'Low cost shallow trench isolation using non-conformal dielectric material'20016,069,049'Shrink-wrap collar from DRAM deep trenches'20005,539,240'Planarized semiconductor structure with subminimum features'19965,466,636'Method of forming borderless contacts using a removable mandrel'19955,453,639'Planarized semiconductor structure using subminimum features'19955,292,689'Method for planarizing semiconductor structure using subminimum features'19945,036,630'Radial uniformity control of semiconductor wafer polishing'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2019Patents assigned to IBM (50)· patent assignee history
1991–2015Based in Underhill, VT, US· patent location history
2012–2015Patents assigned to LANDIS HOWARD S (7)· patent assignee history
2012Patents assigned to COLLINS DAVID S (3)· patent assignee history
2012Patents assigned to LANDIS HOWARD SMITH (3)· patent assignee history
2012Patents assigned to BOTULA ALAN BERNARD (2)· patent assignee history
2015–2019Based in Essex Junction, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 50 | 1991–2019 |
| LANDIS HOWARD Sself | 7 | 2012–2015 |
| COLLINS DAVID S | 3 | 2012 |
| LANDIS HOWARD SMITHself | 3 | 2012 |
| BOTULA ALAN BERNARD | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Underhill, VT, US | 47 | 1991–2015 |
| Essex Junction, VT, US | 3 | 2015–2019 |