Inventor

Mikal C. Hunsaker

Inventor

El Dorado Hills, CA, US

Overview

65→

Patents

1998–2021

Patent span

Physics

Primary field (CPC G)

Patents· 65 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing65%

H04LTransmission of digital information, e.g. telegraphic communication12%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%

G11CStatic stores8%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%

G05BControl or regulating systems in general1%

H04JMultiplex communication1%

H04WWireless communication networks1%

PatentTitleYear

11,119,704System, apparatus and method for sharing a flash device among multiple masters of a computing platform2021 11,113,402Tunneling functional safety communications over an enhanced serial peripheral interface2021 11,086,812Platform environment control interface tunneling via enhanced serial peripheral interface2021 11,036,409Non-volatile memory using a reduced number of interconnect terminals2021 11,016,549Method, apparatus, and system for power management on a CPU die via clock request messaging protocol2021 10,860,500System, apparatus and method for replay protection for a platform component2020 10,853,289System, apparatus and method for hardware-based bi-directional communication via reliable high performance half-duplex link2020 10,719,469Inband messaging method for integrated type-C universal serial bus detection using enhanced serial peripheral interconnect2020 10,229,080Dual bus standard switching bus controller2019 10,185,385Method and apparatus to reduce idle link power in a platform2019 10,164,880Sending packets with expanded headers2018 10,157,160Handling a partition reset in a multi-root system2018 10,146,715Techniques for inter-component communication based on a state of a chip select pin2018 9,921,987'Inter-component communication including posted and non-posted transactions'2018 9,910,814'Method, apparatus and system for single-ended communication of transaction layer packets'2018 9,753,875'Systems and an apparatus with a sideband interface interconnecting agents with at least one router'2017 9,658,978'Providing multiple decode options for a system-on-chip (SoC) fabric'2017 9,619,416'Inter-component communication including posted and non-posted transactions'2017 9,619,628'Secure system flash sharing'2017 9,588,922'Techniques for inter-component communication based on a state of a chip select pin'2017 9,571,215'Measuring time offsets between devices with independent silicon clocks'2017 9,489,329'Supporting multiple channels of a single interface'2016 9,448,870'Providing error handling support to legacy devices'2016 9,418,030'Inter-component communication including posted and non-posted transactions'2016 9,367,116'Apparatus to reduce idle link power in a platform'2016 9,280,198'Method and apparatus to reduce idle link power in a platform'2016 9,274,987'Inter-component communication including slave component initiated transaction'2016 9,270,576'Aggregating completion messages in a sideband interface'2016 9,213,666'Providing a sideband message interface for system on a chip (SoC)'2015 9,176,918'Inter-component communication using an interface including master and slave communication'2015 9,122,815'Common idle state, active state and credit management for an interface'2015 9,098,642'Dual bus standard switching bus controller'2015 9,075,929'Issuing requests to a fabric'2015 9,064,051'Issuing requests to a fabric'2015 9,053,251'Providing a sideband message interface for system on a chip (SoC)'2015 8,929,373'Sending packets with expanded headers'2015 8,892,800'Apparatuses for inter-component communication including slave component initiated transaction'2014 8,874,976'Providing error handling support to legacy devices'2014 8,805,926'Common idle state, active state and credit management for an interface'2014 8,775,700'Issuing requests to a fabric'2014 8,713,234'Supporting multiple channels of a single interface'2014 8,711,875'Aggregating completion messages in a sideband interface'2014 8,713,240'Providing multiple decode options for a system-on-chip (SoC) fabric'2014 8,706,944'Dual bus standard switching bus controller'2014 8,689,028'Method and apparatus to reduce idle link power in a platform'2014 8,386,682'Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform'2013 8,185,072'Method and apparatus for power reduction for interconnect links'2012 8,041,844'Autodetection of a PCI express device operating at a wireless RF mitigation frequency'2011 7,990,999'Starvation prevention scheme for a fixed priority PCE-express arbiter with grant counters using arbitration pools'2011 7,945,719'Controller link for manageability engine'2011 7,694,049'Rate control of flow control updates'2010 7,525,986'Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools'2009 7,296,101'Method and system for using a patch module to process non-posted request cycles and to control completions returned to requesting device'2007 7,191,255'Transaction layer link down handling for PCI express'2007 6,877,060'Dynamic delayed transaction buffer configuration based on bus frequency'2005 6,868,469'Data bridge and bridging'2005 6,782,435'Device for spatially and temporally reordering for data between a processor, memory and peripherals'2004 6,665,756'Bus interface unit for reflecting state information for a transfer request to a requesting device'2003 6,643,716'Method and apparatus for processing serial data using a single receive fifo'2003 6,499,077'Bus interface unit for reflecting state information for a transfer request to a requesting device'2002 6,487,615'Apparatus and method for accepting physical write package when the posted write error queue is full'2002 6,385,671'Method/apparatus for flushing DMA transmit packet in FIFO when self-ID code generated by counter after bus reset is different than FIFO message self-ID field'2002 6,366,968'Physical write packets processing when posted write error queue is full, with posted write error queue storing physical write requests when posted write packet fails'2002 6,199,151'Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle'2001 5,751,998'Memory accessing system with portions of memory being selectively write protectable and relocatable based on predefined register bits and memory selection RAM outputs'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998Based in Houston, TX, US· patent location history

2001–2021Patents assigned to INTEL CORP (64)· patent assignee history

2001–2021Based in El Dorado Hills, CA, US· patent location history

2013–2017Patents assigned to HUNSAKER MIKAL C (12)· patent assignee history

2014–2015Patents assigned to FANNING BLAISE (8)· patent assignee history

2014–2015Patents assigned to KLINGLESMITH MICHAEL T (8)· patent assignee history

2014–2015Patents assigned to LAKSHMANAMURTHY SRIDHAR (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	64	2001–2021
HUNSAKER MIKAL Cself	12	2013–2017
FANNING BLAISE	8	2014–2015
KLINGLESMITH MICHAEL T	8	2014–2015
LAKSHMANAMURTHY SRIDHAR	8	2014–2015

Locations

Location	Patents	Span
El Dorado Hills, California, US	64	2001–2021
Houston, Texas, US	1	1998