Inventor
Shing-Long Lee
Inventor
Hsinchu, TW
Overview
Patents· 9 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1044%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%
G06FElectric digital data processing6%
H01LSemiconductor devices6%
H10DInorganic electric semiconductor devices6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
PatentTitleYear
10,909,302Method, system, and computer program product for characterizing electronic designs with electronic design simplification techniques20219,460,957'Method and structure for nitrogen-doped shallow-trench isolation dielectric'20167,511,936'Method and apparatus for dynamic plasma treatment of bipolar ESC system'20096,926,590'Method of improving device performance'20056,245,666'Method for forming a delamination resistant multi-layer dielectric layer for passivating a conductor layer'20015,943,582'Method for forming DRAM stacked capacitor'19995,877,092'Method for edge profile and design rules control'19995,872,061'Plasma etch method for forming residue free fluorine containing plasma etched layers'19995,783,482'Method to prevent oxide peeling induced by sog etchback on the wafer edge'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2009Patents assigned to TAIWAN SEMICONDUCTOR MFG (7)· patent assignee history
1998Based in Shin-Chu, TW· patent location history
1999–2016Based in Hsinchu, TW· patent location history
2009Based in Nei Hu, TW· patent location history
2016Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (1)· patent assignee history
2021Patents assigned to CADENCE DESIGN SYSTEMS INC (1)· patent assignee history
2021Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 7 | 1998–2009 |
| CADENCE DESIGN SYSTEMS INC | 1 | 2021 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 6 | 1999–2016 |
| San Jose, California, US | 1 | 2021 |
| Nei Hu, TW | 1 | 2009 |
| Shin-Chu, TW | 1 | 1998 |