Inventor
SENAKA KANAKAMEDALA
Inventor
US
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices30%
H01LSemiconductor devices26%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H10DInorganic electric semiconductor devices12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
G11CStatic stores3%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
12,598,752Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202612,581,656Three-dimensional memory device and method of making thereof using etch stop structures located between tiers202612,581,652Three-dimensional memory devices having channel cap structures and methods for forming the same202612,512,366Method of making high aspect ratio openings in a semiconductor device using ion implanted regrown cladding mask202512,484,222Three-dimensional memory device and method of making thereof by non-conformal selective deposition of insulating spacers in a memory opening202512,426,267Three-dimensional memory device and method of making thereof using sacrificial material regrowth202512,387,976Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202512,317,502Three-dimensional memory device containing ferroelectric-assisted memory elements and method of making the same202512,267,998Three-dimensional memory device including discrete charge storage elements and methods of forming the same202512,261,080Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202512,245,434Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202512,243,776Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202512,160,989Three-dimensional memory device including an isolation-trench etch stop layer and methods for forming the same202412,150,302Memory device including mixed oxide charge trapping materials and methods for forming the same202412,010,841Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202411,972,954Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202411,968,826Three-dimensional memory device with metal-barrier-metal word lines and methods of making the same202411,968,834Three-dimensional memory device including discrete charge storage elements with laterally-protruding profiles and methods of making thereof202411,749,736Three-dimensional memory device including discrete charge storage elements and methods for forming the same202311,631,686Three-dimensional memory array including dual work function floating gates and method of making the same202311,621,277Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof202311,515,250Three dimensional semiconductor device containing composite contact via structures and methods of making the same202211,515,273Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same202211,489,043Three-dimensional memory device employing thinned insulating layers and methods for forming the same202211,482,531Three-dimensional memory device including multi-bit charge storage elements and methods for forming the same202211,469,241Three-dimensional memory device including discrete charge storage elements and methods of forming the same202211,450,687Multibit ferroelectric memory cells and methods for forming the same202211,430,736Semiconductor device including having metal organic framework interlayer dielectric layer between metal lines and methods of forming the same202211,398,496Three-dimensional memory device employing thinned insulating layers and methods for forming the same202211,393,780Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same202211,387,250Three-dimensional memory device containing metal-organic framework inter-word line insulating layers202211,387,244Three-dimensional memory device including discrete charge storage elements and methods of forming the same202211,296,028Semiconductor device containing metal-organic framework inter-line insulator structures and methods of manufacturing the same202211,296,101Three-dimensional memory device including an inter-tier etch stop layer and method of making the same202211,244,953Three-dimensional memory device including molybdenum word lines and metal oxide spacers and method of making the same202211,201,139Semiconductor structure containing reentrant shaped bonding pads and methods of forming the same202111,145,628Semiconductor structure containing reentrant shaped bonding pads and methods of forming the same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to SANDISK TECHNOLOGIES LLC (35)· patent assignee history
2021–2026Based in US· patent location history
2025–2026Patents assigned to SANDISK TECHNOLOGIES INC (11)· patent assignee history
2025Patents assigned to WESTERN DIGITAL TECH INC (1)· patent assignee history
2026Patents assigned to SANDISK TECH INC (1)· patent assignee history
2026Patents assigned to SANDISK TECH LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 35 | 2021–2026 |
| SANDISK TECHNOLOGIES INC | 11 | 2025–2026 |
| SANDISK TECH INC | 1 | 2026 |
| SANDISK TECH LLC | 1 | 2026 |
| WESTERN DIGITAL TECH INC | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 37 | 2021–2026 |