Inventor
Chungho Lee
Inventor
Sunnyvale, CA, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
H10BElectronic memory devices27%
H01LSemiconductor devices8%
G11CStatic stores5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
B82YSpecific uses or applications of nanostructures2%
PatentTitleYear
9,640,679'Photovoltaic device with oxide layer'20179,508,874'Photovoltaic device and method of manufacture'20169,461,151'Dual storage node memory'20169,245,895'Oro and orpro with bit line trench to suppress transport program disturb'20169,159,568'Method for fabricating memory cells having split charge storage nodes'20158,564,042'Dual storage node memory'20138,455,268'Gate replacement with top oxide regrowth for the top oxide improvement'20138,329,598'Sacrificial nitride and gate replacement'20128,183,623'Dual charge storage node memory device and methods for fabricating such device'20128,076,712'Semiconductor memory comprising dual charge storage nodes and methods for its fabrication'20118,039,891'Split charge storage node outer spacer process'20118,012,830'ORO and ORPRO with bit line trench to suppress transport program disturb'20117,981,745'Sacrificial nitride and gate replacement'20117,960,776'Transistor with floating gate and electret'20117,951,675'SI trench between bitline HDP for BVDSS improvement'20117,915,123'Dual charge storage node memory device and methods for fabricating such device'20117,883,963'Split charge storage node outer spacer process'20117,829,936'Split charge storage node inner spacer process'20107,807,580'Triple poly-si replacement scheme for memory devices'20107,767,517'Semiconductor memory comprising dual charge storage nodes and methods for its fabrication'20107,666,739'Methods for fabricating a split charge storage node semiconductor memory'20107,622,373'Memory device having implanted oxide to block electron drift, and method of manufacturing the same'20097,564,091'Memory device and methods for its fabrication'20097,432,156'Memory device and methods for its fabrication'20087,259,984'Multibit metal nanocrystal memories and fabrication'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2011Based in Ithaca, NY, US· patent location history
2008–2013Patents assigned to SPANSION LLC (18)· patent assignee history
2008–2016Based in Sunnyvale, CA, US· patent location history
2011–2017Patents assigned to LEE CHUNGHO (8)· patent assignee history
2011–2015Patents assigned to KINOSHITA HIROYUKI (6)· patent assignee history
2011–2015Patents assigned to CHANG CHI (5)· patent assignee history
2011–2016Patents assigned to CHANG KUO-TUNG (5)· patent assignee history
2016–2017Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SPANSION LLC | 18 | 2008–2013 |
| LEE CHUNGHOself | 8 | 2011–2017 |
| KINOSHITA HIROYUKI | 6 | 2011–2015 |
| CHANG CHI | 5 | 2011–2015 |
| CHANG KUO-TUNG | 5 | 2011–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 21 | 2008–2016 |
| San Jose, California, US | 2 | 2016–2017 |
| Ithaca, New York, US | 2 | 2007–2011 |