Inventor
William C. Wille
Inventor
Red Hook, NY, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10DInorganic electric semiconductor devices21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
B81BMicrostructural devices or systems, e.g. micromechanical devices6%
H01HElectric switches6%
H10BElectronic memory devices6%
B24BMachines, devices, or processes for grinding or polishing3%
B82YSpecific uses or applications of nanostructures3%
C23CCoating metallic material3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
PatentTitleYear
7,838,390'Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein'20107,635,899'Structure and method to form improved isolation in a semiconductor device'20097,550,364'Stress engineering using dual pad nitride with selective SOI device architecture'20097,202,513'Stress engineering using dual pad nitride with selective SOI device architecture'20077,183,130'Magnetic random access memory and method of fabricating thereof'20077,030,031'Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material'20066,762,667'Micro electromechanical switch having self-aligned spacers'20046,621,392'Micro electromechanical switch having self-aligned spacers'20036,593,617'Field effect transistors with vertical gate side walls and method for making such transistors'20036,461,529'Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme'20026,361,402'Method for planarizing photoresist'20026,207,353'Resist formulation which minimizes blistering during etching'20016,143,635'Field effect transistors with improved implants and method for making such transistors'20006,093,281'Baffle plate design for decreasing conductance lost during precipitation of polymer precursors in plasma etching chambers'20006,040,214'Method for making field effect transistors having sub-lithographic gates with vertical side walls'20005,976,982'Methods for protecting device components from chemical mechanical polish induced defects'19995,811,357'Process of etching an oxide layer'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2009Patents assigned to IBM (16)· patent assignee history
1998Based in Poughkeepsie, NY, US· patent location history
1999Patents assigned to SIEMENS AG (1)· patent assignee history
1999–2010Based in Red Hook, NY, US· patent location history
2000–2003Based in Red Creek, NY, US· patent location history
2010Patents assigned to SAMSUNG ELECTRONICS CO LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 16 | 1998–2009 |
| SAMSUNG ELECTRONICS CO LTD | 1 | 2010 |
| SIEMENS AG | 1 | 1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| Red Hook, New York, US | 13 | 1999–2010 |
| Red Creek, New York, US | 3 | 2000–2003 |
| Poughkeepsie, New York, US | 1 | 1998 |