LexDanaLexDanabeta
Inventor

Kwan-Yong Lim

Inventor
Niskayuna, NY, US

Overview

104→
Patents
2002–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 104 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices39%
H01LSemiconductor devices21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10BElectronic memory devices12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
G11CStatic stores1%
G06FElectric digital data processing1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
Y10TTechnical subjects covered by former us classification1%
B82YSpecific uses or applications of nanostructures0%
PatentTitleYear
10,879,171Vertically oriented metal silicide containing e-fuse device202010,580,779Vertical transistor static random access memory cell202010,529,724Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures202010,510,662Vertically oriented metal silicide containing e-fuse device and methods of making same201910,468,481Self-aligned single diffusion break isolation with reduction of strain loss201910,297,672Triple gate technology for 14 nanometer and onwards201910,290,738Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device201910,243,073Vertical channel field-effect transistor (FET) process compatible long channel transistors201910,236,291Methods, apparatus and system for STI recess control for highly scaled finFET devices201910,163,900Integration of vertical field-effect transistors and saddle fin-type field effect transistors201810,141,446Formation of bottom junction in vertical FET devices201810,121,868Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET device201810,083,971Vertical SRAM structure with cross-coupling contacts penetrating through common gates to bottom S/D metal contacts201810,068,978Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression201810,008,499Method to form silicide and contact at embedded epitaxial facet20189,960,086Methods, apparatus and system for self-aligned retrograde well doping for finFET devices20189,929,236'Active area shapes reducing device size'20189,911,738'Vertical-transport field-effect transistors with a damascene gate strap'20189,865,704'Single and double diffusion breaks on integrated circuit products comprised of FinFET devices'20189,859,125'Block patterning method enabling merged space in SRAM with heterogeneous mandrel'20189,847,418Methods of forming fin cut regions by oxidizing fin portions20179,842,933'Formation of bottom junction in vertical FET devices'20179,837,404Methods, apparatus and system for STI recess control for highly scaled finFET devices20179,812,452'Method to form silicide and contact at embedded epitaxial facet'20179,799,751'Methods of forming a gate structure on a vertical transistor device'20179,773,708'Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI'20179,761,662'Active area shapes reducing device size'20179,711,511'Vertical channel transistor-based semiconductor memory structure'20179,640,533'Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression'20179,640,636'Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device'20179,543,215'Punch-through-stop after partial fin etch'20179,536,793'Self-aligned gate-first VFETs using a gate spacer recess'20179,530,863'Methods of forming vertical transistor devices with self-aligned replacement gate structures'20169,530,866'Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts'20169,508,601'Method to form silicide and contact at embedded epitaxial facet'20169,419,131'Semiconductor device having vertical channel transistor and method for fabricating the same'20169,412,616'Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products'20169,406,769'Silicide formation due to improved SiGe faceting'20169,362,279'Contact formation for semiconductor device'20169,362,181'Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products'20169,324,799'FinFET structures having uniform channel size and methods of fabrication'20169,263,446'Methods of forming replacement gate structures on transistor devices with a shared gate structure and the resulting products'20169,245,975'Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length'20169,240,404'Embedded polysilicon resistor in integrated circuits formed by a replacement gate process'20169,236,308'Methods of fabricating fin structures of uniform height'20169,236,452'Raised source/drain EPI with suppressed lateral EPI overgrowth'20169,202,883'Silicide formation due to improved SiGe faceting'20159,178,038'Raised source/drain MOS transistor and method of forming the transistor with an implant spacer and an epitaxial spacer'20159,093,298'Silicide formation due to improved SiGe faceting'20159,064,854'Semiconductor device with gate stack structure'20158,865,542'Embedded polysilicon resistor in integrated circuits formed by a replacement gate process'20148,865,549'Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length'20148,847,322'Dual polysilicon gate of a semiconductor device with a multi-plane channel'20148,759,906'Semiconductor device having vertical channel transistor and method for fabricating the same'20148,633,078'Method for manufacturing semiconductor device'20148,471,338'Dual polysilicon gate of a semiconductor device with a multi-plane channel'20138,440,560'Method for fabricating tungsten line and method for fabricating gate of semiconductor device using the same'20138,441,079'Semiconductor device with gate stack structure'20138,395,266'Semiconductor memory device'20138,330,215'Transistor including bulb-type recess channel and method for fabricating the same'20128,330,211'Semiconductor device with vertical channel transistor and low sheet resistance and method for fabricating the same'20128,319,341'Semiconductor device with gate structure'20128,288,819'Semiconductor device with bulb-type recessed channel and method for fabricating the same'20128,237,220'Semiconductor device with vertical channel transistor'20128,227,920'Semiconductor device and method for fabricating the same'20128,101,480'Methods of forming transistors and CMOS semiconductor devices using an SMT technique'20128,053,841'Semiconductor device having a fin transistor'20118,048,742'Transistor including bulb-type recess channel and method for fabricating the same'20118,049,268'Dielectric structure in nonvolatile memory device and method for fabricating the same'20118,021,969'Semiconductor device and method for fabricating the same'20118,008,178'Method for fabricating semiconductor device with an intermediate stack structure'20117,994,558'Method for forming barrier metal layer of bit line in semiconductor memory device'20117,902,614'Semiconductor device with gate stack structure'20117,838,364'Semiconductor device with bulb-type recessed channel and method for fabricating the same'20107,825,014'Method for fabricating semiconductor device'20107,781,333'Semiconductor device with gate structure and method for fabricating the semiconductor device'20107,741,170'Dielectric structure in nonvolatile memory device and method for fabricating the same'20107,713,823'Semiconductor device with vertical channel transistor and method for fabricating the same'20107,687,389'Method for fabricating semiconductor device'20107,682,911'Semiconductor device having a fin transistor and method for fabricating the same'20107,666,785'Method for fabricating semiconductor device with interface barrier'20107,667,253'Non-volatile memory device with conductive sidewall spacer and method for fabricating the same'20107,629,219'Method of fabricating a dual polysilicon gate of a semiconductor device with a multi-plane channel'20097,563,726'Semiconductor device with multiple gate dielectric layers and method for fabricating the same'20097,541,269'Method of forming tungsten polymetal gate having low resistance'20097,528,042'Method for fabricating semiconductor devices having dual gate oxide layer'20097,271,066'Semiconductor device and a method of manufacturing the same'20077,217,624'Non-volatile memory device with conductive sidewall spacer and method for fabricating the same'20077,157,339'Method for fabricating semiconductor devices having dual gate oxide layers'20077,157,359'Method of forming a metal gate in a semiconductor device using atomic layer deposition process'20077,145,207'Gate structure of semiconductor memory device'20067,112,486'Method for fabricating semiconductor device by using radical oxidation'20067,081,390'Semiconductor device and a method of manufacturing the same'20067,074,661'Method for fabricating semiconductor device with use of partial gate recessing process'20067,029,999'Method for fabricating transistor with polymetal gate electrode'20066,987,056'Method of forming gates in semiconductor devices'20066,979,616'Method for fabricating semiconductor device with dual gate dielectric structure'20056,936,529'Method for fabricating gate-electrode of semiconductor device with use of hard mask'20056,828,185'CMOS of semiconductor device and method for manufacturing the same'20046,768,179'CMOS of semiconductor device and method for manufacturing the same'20046,734,113'Method for forming multiple gate oxide layers'20046,642,132'Cmos of semiconductor device and method for manufacturing the same'20036,506,676'Method of manufacturing semiconductor devices with titanium aluminum nitride work function'20036,448,166'Method for forming a gate for semiconductor devices'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2014Patents assigned to HYNIX SEMICONDUCTOR INC (48)· patent assignee history
2002–2009Based in Kyungki-do, KR· patent location history
2004–2015Based in Ichon-shi, KR· patent location history
2009–2016Based in Icheon-si, KR· patent location history
2012–2014Patents assigned to LIM KWAN-YONG (12)· patent assignee history
2012–2014Patents assigned to SUNG MIN-GYU (10)· patent assignee history
2014–2018Patents assigned to TEXAS INSTRUMENTS INC (11)· patent assignee history
2014–2018Based in Plano, TX, US· patent location history
2016–2020Patents assigned to GLOBALFOUNDRIES INC (38)· patent assignee history
2016–2020Based in Niskayuna, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
HYNIX SEMICONDUCTOR INC482002–2014
GLOBALFOUNDRIES INC382016–2020
LIM KWAN-YONGself122012–2014
TEXAS INSTRUMENTS INC112014–2018
SUNG MIN-GYU102012–2014
Locations
LocationPatentsSpan
Niskayuna, New York, US362016–2020
Ichon-shi, KR352004–2015
Plano, Texas, US112014–2018
Kyungki-do, KR102002–2009
Icheon-si, KR32009–2016