Inventor
VIOLANTE MOSCHIANO
Inventor
IT
Overview
Patents· 61 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores59%
G06FElectric digital data processing34%
H03MCoding4%
H01LSemiconductor devices1%
H10BElectronic memory devices1%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
PatentTitleYear
12,562,227Voltage regulator supply for independent wordline reads202612,542,188Boost-by-deck during a program operation on a memory device202612,517,655Program command generation with dummy data generation at a memory device202612,482,523Configuration of a memory device for programming memory cells202512,431,197Programming operation using cache register release in a memory sub-system202512,423,002Selectively programming retired wordlines of a memory device202512,411,770Hybrid parallel programming of single-level cell memory202512,373,109Validating read level voltage in memory devices202512,340,851Memories for performing successive programming operations202512,334,142Sacrificial strings in a memory device to detect read disturb202512,327,595Shortened single-level cell memory programming202512,322,440Programming operation of memory device being switched from high-density mode to high speed mode and/or lower power mode202512,315,574Auto-calibrated corrective read202512,315,573Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device202512,315,575Boost voltage modulated corrective read202512,265,447Memory sub-system with dynamic calibration using component-based function(s)202512,217,799Parallelized defect detection across multiple sub-blocks in a memory device202512,205,653Wordline or pillar state detection for faster read access times202512,170,113Concurrent programming of retired wordline cells with dummy data202412,148,466Determining soft data202412,142,318Redundancy and majority voting in a key-value data storage system using content addressable memory202412,141,437Program command generation with dummy data generation at a memory device202412,131,028Programming selective word lines during an erase operation in a memory device202412,105,961Copyback clear command for performing a scan and read in a memory device202412,094,547Continuous memory programming operations202412,087,372Partial block erase operations in memory devices202412,073,891Integrated command to calibrate read voltage level202412,067,290On-die cross-temperature management for a memory device202412,051,484Memory device with adjustable delay propagation of a control signal to different page buffer driver groups202412,001,336Hybrid parallel programming of single-level cell memory202411,955,175Copy redundancy in a key-value data storage system using content addressable memory202411,955,204Apparatuses and methods for concurrently accessing different memory planes of a memory202411,953,980Memory sub-system with dynamic calibration using component-based function(s)202411,908,523Express programming using advanced cache register release in a memory sub-system202411,899,966Implementing fault tolerant page stripes on low density memory systems202411,862,257Managing programming convergence associated with memory cells of a memory sub-system202411,842,774Memories for calibrating sensing of memory cell data states202311,810,613Ultra-compact page buffer202311,776,633Apparatus and methods for determining data states of memory cells202311,762,767Storing highly read data at low impact read disturb pages of a memory device202311,721,396Configuration of a memory device for programming memory cells202311,715,547Scan optimization using data selection across wordline of a memory array202311,688,459Determining soft data202311,688,466Bitline driver isolation from page buffer circuitry in memory device202311,688,474Dual verify for quick charge loss reduction in memory cells202311,662,905Memory system performance enhancements using measured signal and noise characteristics of memory cells202311,636,908Global-local read calibration202311,605,588Memory device including data lines on multiple device levels202311,532,367Managing programming convergence associated with memory cells of a memory sub-system202211,526,393Memory sub-system with dynamic calibration using component-based function(s)202211,475,969Scan optimization using data selection across wordline of a memory array202211,462,250Apparatuses and methods for concurrently accessing different memory planes of a memory202211,450,379Ultra-compact page buffer202211,449,271Implementing fault tolerant page stripes on low density memory systems202211,437,093Methods for mitigating power loss events during operation of memory devices and memory devices employing the same202211,309,039Apparatus for determining a pass voltage of a read operation202211,276,470Bitline driver isolation from page buffer circuitry in memory device202211,270,774Apparatus for calibrating sensing of memory cell data states202211,237,726Memory system performance enhancements using measured signal and noise characteristics of memory cells202211,177,014Global-local read calibration202111,163,572Memory systems and memory control methods2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (59)· patent assignee history
2021–2026Based in IT· patent location history
2025Patents assigned to Intel NDTM US LLC (1)· patent assignee history
2025Patents assigned to LODESTAR LICENSING GROUP LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 59 | 2021–2026 |
| Intel NDTM US LLC | 1 | 2025 |
| LODESTAR LICENSING GROUP LLC | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| IT | 61 | 2021–2026 |