Inventor
Uwe Brandt
Inventor
Stuttgart, DE
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing69%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%
A23BPreservation of foods, foodstuffs or non-alcoholic beverages6%
A23LFoods, foodstuffs or non-alcoholic beverages, not otherwise provided for6%
G11CStatic stores3%
H01TSpark gaps3%
PatentTitleYear
11,036,647Suspending translation look-aside buffer purge execution in a multi-processor environment202110,956,341Multi-engine address translation facility202110,929,312Zone-SDID mapping scheme for TLB purges202110,698,835Suspending translation look-aside buffer purge execution in a multi-processor environment202010,635,603Multi-engine address translation facility202010,621,105Multi-engine address translation facility202010,387,326Incorporating purge history into least-recently-used states of a translation lookaside buffer201910,380,032Multi-engine address translation facility201910,380,033Multi-engine address translation facility201910,353,827Zone-SDID mapping scheme for TLB purges201910,353,825Suspending translation look-aside buffer purge execution in a multi-processor environment201910,353,828Zone-SDID mapping scheme for TLB purges201910,289,562Incorporating purge history into least-recently-used states of a translation lookaside buffer201910,248,575Suspending translation look-aside buffer purge execution in a multi-processor environment201910,140,217Link consistency in a hierarchical TLB with concurrent table walks201810,127,159Link consistency in a hierarchical TLB with concurrent table walks201810,083,124Translating virtual memory addresses to physical addresses20189,886,395'Evicting cached stores'20189,720,764'Uncorrectable memory errors in pipelined CPUs'20179,658,967'Evicting cached stores'20179,588,894'Store cache for transactional memory'20179,588,893'Store cache for transactional memory'20178,756,538'Parsing data representative of a hardware design into commands of a hardware design environment'20148,560,983'Incorporating synthesized netlists as subcomponents in a hierarchical custom design'20137,844,871'Test interface for memory elements'20105,427,810'Method for hydrothermal treatment of starch products, particularly rice'19955,293,814'Apparatus for hydro-thermical treatment of starchy products, in particular rice'19945,180,313'Ground connection for the spark plugs of a multi-cylinder internal-combustion vehicle engine'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2013Patents assigned to BRANDT UWE (2)· patent assignee history
1993Based in Ludenscheid, DE· patent location history
1994–1995Patents assigned to BUEHLER GMBH (2)· patent assignee history
1994–1995Based in Braunschweig, DE· patent location history
2010–2021Patents assigned to IBM (25)· patent assignee history
2010–2019Based in Boeblingen, DE· patent location history
2013Patents assigned to MAKOWSKI THOMAS M (1)· patent assignee history
2013Patents assigned to WANDEL CHRISTOPH (1)· patent assignee history
2017–2021Based in Stuttgart, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 25 | 2010–2021 |
| BRANDT UWEself | 2 | 1993–2013 |
| BUEHLER GMBH | 2 | 1994–1995 |
| MAKOWSKI THOMAS M | 1 | 2013 |
| WANDEL CHRISTOPH | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Stuttgart, DE | 16 | 2017–2021 |
| Boeblingen, DE | 9 | 2010–2019 |
| Braunschweig, DE | 2 | 1994–1995 |
| Ludenscheid, DE | 1 | 1993 |