Inventor

Nima Mokhlesi

Inventor

Los Gatos, CA, US

Overview

2002–2019

Patent span

Physics

Primary field (CPC G)

Patents· 181 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores59%

H10BElectronic memory devices17%

H10DInorganic electric semiconductor devices11%

G06FElectric digital data processing6%

B82YSpecific uses or applications of nanostructures2%

H03MCoding2%

H01LSemiconductor devices2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h100%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h100%

PatentTitleYear

RE047226Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution2019 10,157,681Programming of nonvolatile memory with verify level dependent on memory state and programming loop count2018 RE046995Programming non-volatile storage using binary and multi-state programming processes2018 9,947,682Three dimensional non-volatile memory with separate source lines2018 9,911,488'Three dimensional non-volatile memory with shorting source line/bit line pairs'2018 RE046573'Simultaneous multi-state read or verify in non-volatile storage'2017 RE046498'Reducing energy consumption when applying body bias to substrate having sets of NAND strings'2017 9,715,924'Three dimensional non-volatile memory with current sensing programming status'2017 9,570,185'Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution'2017 9,570,184'Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution'2017 RE046279'Read operation for non-volatile storage with compensation for coupling'2017 9,076,544'Operation for non-volatile storage system with shared bit lines'2015 9,076,545'Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution'2015 9,070,472'Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling'2015 9,070,475'Reading soft bits simultaneously'2015 9,047,971'Operation for non-volatile storage system with shared bit lines'2015 9,036,416'Non-volatile storage with broken word line screen and data recovery'2015 8,966,350'Providing reliability metrics for decoding data in non-volatile storage'2015 8,873,285'Simultaneous multi-level binary search in non-volatile storage'2014 8,837,216'Non-volatile storage system with shared bit lines connected to a single selection device'2014 8,531,889'Non-volatile memory and method with improved sensing having bit-line lockout control'2013 8,509,000'Simultaneous multi-state read or verify in non-volatile storage'2013 8,498,152'Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling'2013 8,472,255'Compensation of non-volatile memory chip non-idealities by program pulse adjustment'2013 8,468,424'Method for decoding data in non-volatile storage using reliability metrics based on multiple reads'2013 8,427,873'Read operation for non-volatile storage with compensation for coupling'2013 8,406,063'Programming non-volatile storage with synchonized coupling'2013 8,400,854'Identifying at-risk data in non-volatile storage'2013 8,395,945'Variable initial program voltage magnitude for non-volatile storage'2013 8,368,137'Dual bit line metal layers for non-volatile memory'2013 8,288,225'Method of reducing coupling between floating gates in nonvolatile memory'2012 8,284,609'Compensation of non-volatile memory chip non-idealities by program pulse adjustment'2012 8,274,831'Programming non-volatile storage with synchronized coupling'2012 8,264,890'Two pass erase for non-volatile storage'2012 8,248,859'Methods of forming and operating NAND memory with side-tunneling'2012 8,233,324'Simultaneous multi-state read or verify in non-volatile storage'2012 8,199,571'Read operation for non-volatile storage with compensation for coupling'2012 8,179,723'Non-volatile memory with boost structures'2012 8,164,957'Reducing energy consumption when applying body bias to substrate having sets of nand strings'2012 8,154,921'Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution'2012 8,143,156'Methods of forming high density semiconductor devices using recursive spacer technique'2012 8,145,981'Soft bit data transmission for error correction control in non-volatile memory'2012 8,125,832'Variable initial program voltage magnitude for non-volatile storage'2012 8,111,548'Programming non-volatile storage using binary and multi-state programming processes'2012 8,097,504'Method for forming dual bit line metal layers for non-volatile memory'2012 8,098,526'Reverse reading in non-volatile memory with compensation for coupling'2012 8,098,537'Data refresh for non-volatile storage'2012 8,045,391'Non-volatile memory and method with improved sensing having bit-line lockout control'2011 8,026,170'Method of forming a single-layer metal conductors with multiple thicknesses'2011 8,014,197'System and method for programming cells in non-volatile integrated memory devices'2011 8,000,146'Applying different body bias to different substrate portions for non-volatile storage'2011 7,978,520'Compensation of non-volatile memory chip non-idealities by program pulse adjustment'2011 7,975,209'Non-volatile memory with guided simulated annealing error correction control'2011 7,971,127'Guided simulated annealing in non-volatile memory error correction control'2011 7,966,546'Non-volatile memory with soft bit data transmission for error correction control'2011 7,966,550'Soft bit data transmission for error correction control in non-volatile memory'2011 7,957,187'Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution'2011 7,920,422'All-bit-line erase verify and soft program verify'2011 7,910,434'Method of reducing coupling between floating gates in nonvolatile memory'2011 7,911,838'Read operation for non-volatile storage with compensation for coupling'2011 7,907,449'Two pass erase for non-volatile storage'2011 7,904,793'Method for decoding data in non-volatile storage using reliability metrics based on multiple reads'2011 7,885,112'Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages'2011 7,877,665'Page by page ECC variation in a memory device'2011 7,876,620'Read disturb mitigation in non-volatile memory'2011 7,870,457'Page by page ECC variation in a memory device'2011 7,859,932'Data refresh for non-volatile storage'2010 7,851,851'Three dimensional NAND memory'2010 7,848,145'Three dimensional NAND memory'2010 7,834,386'Non-volatile memory with epitaxial regions for limiting cross coupling between floating gates'2010 7,807,533'Method for forming non-volatile memory with shield plate for limiting cross coupling between floating gates'2010 7,808,832'Non-volatile memory and method with improved sensing having a bit-line lockout control'2010 7,808,831'Read disturb mitigation in non-volatile memory'2010 7,808,038'Method of making three dimensional NAND memory'2010 7,799,637'Scaled dielectric enabled by stack sidewall process'2010 7,800,161'Flash NAND memory cell array with charge storage elements positioned in trenches'2010 7,797,480'Method for reading non-volatile storage using pre-conditioning waveforms and modified reliability metrics'2010 7,778,106'Read operation for non-volatile storage with compensation for coupling'2010 7,764,547'Regulation of source potential to combat cell source IR drop'2010 7,764,544'All-bit-line erase verify and soft program verify'2010 7,755,132'Nonvolatile memories with shaped floating gates'2010 7,751,244'Applying adaptive body bias to non-volatile storage based on number of programming cycles'2010 7,745,265'Method of making three dimensional NAND memory'2010 7,745,285'Methods of forming and operating NAND memory with side-tunneling'2010 7,734,861'Pseudo random and command driven bit compensation for the cycling effects in flash memory'2010 7,696,035'Method for fabricating non-volatile memory with boost structures'2010 7,696,044'Method of making an array of non-volatile memory cells with floating gates formed of spacers in substrate trenches'2010 7,691,710'Fabricating non-volatile memory with dual voltage select gate structure'2010 7,684,247'Reverse reading in non-volatile memory with compensation for coupling'2010 7,646,054'Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches'2010 7,642,160'Method of forming a flash NAND memory cell array with charge storage elements positioned in trenches'2010 7,633,802'Non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages'2009 7,630,237'System and method for programming cells in non-volatile integrated memory devices'2009 7,619,930'Dynamic verify based on threshold voltage distribution'2009 7,616,500'Non-volatile storage apparatus with multiple pass write sequence'2009 7,615,445'Methods of reducing coupling between floating gates in nonvolatile memory'2009 7,616,490'Programming non-volatile memory with dual voltage select gate structure'2009 7,616,495'Non-volatile storage apparatus with variable initial program voltage magnitude'2009 7,616,481'Memories with alternate sensing techniques'2009 7,616,498'Non-volatile storage system with resistance sensing and compensation'2009 7,613,068'Read operation for non-volatile storage with compensation for coupling'2009 7,606,966'Methods in a pseudo random and command driven bit compensation for the cycling effects in flash memory'2009 7,606,072'Non-volatile storage with compensation for source voltage drop'2009 7,606,079'Reducing power consumption during read operations in non-volatile storage'2009 7,606,070'Systems for margined neighbor reading for non-volatile memory read operations including coupling compensation'2009 7,606,071'Compensating source voltage drop in non-volatile storage'2009 7,590,002'Resistance sensing and compensation for non-volatile storage'2009 7,586,157'Non-volatile memory with dual voltage select gate structure'2009 7,583,539'Non-volatile storage with bias for temperature compensation'2009 7,583,535'Biasing non-volatile storage to compensate for temperature variations'2009 7,575,973'Method of making three dimensional NAND memory'2009 7,577,031'Non-volatile memory with compensation for variations along a word line'2009 7,564,711'Multiple pass write sequence for non-volatile storage'2009 7,564,715'Variable initial program voltage magnitude for non-volatile storage'2009 7,561,473'System for performing data pattern sensitivity compensation using different voltage'2009 7,554,853'Non-volatile storage with bias based on selective word line'2009 7,551,477'Multiple bit line voltages based on distance'2009 7,535,764'Adjusting resistance of non-volatile memory using dummy memory cells'2009 7,532,516'Non-volatile storage with current sensing of negative threshold voltages'2009 7,525,843'Non-volatile storage with adaptive body bias'2009 7,518,928'Efficient verification for coarse/fine programming of non volatile memory'2009 7,518,923'Margined neighbor reading for non-volatile memory read operations including coupling compensation'2009 7,514,321'Method of making three dimensional NAND memory'2009 7,512,005'NAND memory with side-tunneling'2009 7,508,713'Method of compensating variations along a word line in a non-volatile memory'2009 7,508,703'Non-volatile memory with boost structures'2009 7,508,710'Operating non-volatile memory with boost structures'2009 7,499,319'Read operation for non-volatile storage with compensation for coupling'2009 7,494,860'Methods of forming nonvolatile memories with L-shaped floating gates'2009 7,495,962'Alternating read mode'2009 7,492,640'Sensing with bit-line lockout control in non-volatile memory'2009 7,492,633'System for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines'2009 7,489,549'System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages'2009 7,489,553'Non-volatile memory with improved sensing having bit-line lockout control'2009 7,486,561'Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages'2009 7,468,919'Biasing non-volatile storage based on selected word line'2008 7,468,920'Applying adaptive body bias to non-volatile storage'2008 7,468,921'Method for increasing programming speed for non-volatile memory by applying direct-transitioning waveforms to word lines'2008 7,463,528'Temperature compensation of select gates in non-volatile memory'2008 7,460,407'Temperature compensation of voltages of unselected word lines in non-volatile memory based on word line position'2008 7,460,406'Alternate sensing techniques for non-volatile memories'2008 7,453,730'Charge packet metering for coarse/fine programming of non-volatile memory'2008 7,450,421'Data pattern sensitivity compensation using different voltage'2008 7,447,075'Charge packet metering for coarse/fine programming of non-volatile memory'2008 7,447,076'Systems for reverse reading in non-volatile memory with compensation for coupling'2008 7,447,079'Method for sensing negative threshold voltages in non-volatile storage using current sensing'2008 7,440,324'Apparatus with alternating read mode'2008 7,440,327'Non-volatile storage with reduced power consumption during read operations'2008 7,436,733'System for performing read operation on non-volatile storage with compensation for coupling'2008 7,425,744'Fabricating logic and memory elements using multiple gate layers'2008 7,414,887'Variable current sinking for coarse/fine programming of non-volatile memory'2008 7,411,827'Boosting to control programming of non-volatile memory'2008 7,405,968'Non-volatile memory cell using high-K material and inter-gate programming'2008 7,403,421'Noise reduction technique for transistors and small devices utilizing an episodic agitation'2008 7,397,707'Compressed event counting technique and application to a flash memory system'2008 7,391,650'Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates'2008 7,355,237'Shield plate for limiting cross coupling between floating gates'2008 7,349,261'Method for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines'2008 7,349,264'Alternate sensing techniques for non-volatile memories'2008 7,342,831'System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates'2008 7,317,638'Efficient verification for coarse/fine programming of non-volatile memory'2008 7,310,272'System for performing data pattern sensitivity compensation using different voltage'2007 7,301,812'Boosting to control programming of non-volatile memory'2007 7,280,408'Bitline governed approach for programming non-volatile memory'2007 7,265,423'Technique for fabricating logic elements using multiple gate layers'2007 7,253,055'Pillar cell flash memory technology'2007 7,154,779'Non-volatile memory cell using high-k material inter-gate programming'2006 7,139,198'Efficient verification for coarse/fine programming of non-volatile memory'2006 7,113,432'Compressed event counting technique and application to a flash memory system'2006 7,092,292'Noise reduction technique for transistors and small devices utilizing an episodic agitation'2006 7,088,621'Bitline governed approach for coarse/fine programming'2006 7,068,539'Charge packet metering for coarse/fine programming of non-volatile memory'2006 7,064,034'Technique for fabricating logic elements using multiple gate layers'2006 7,049,652'Pillar cell flash memory technology'2006 7,023,733'Boosting to control programming of non-volatile memory'2006 7,020,026'Bitline governed approach for program control of non-volatile memory'2006 7,002,843'Variable current sinking for coarse/fine programming of non-volatile memory'2006 6,856,551'System and method for programming cells in non-volatile integrated memory devices'2005 6,850,441'Noise reduction technique for transistors and small devices utilizing an episodic agitation'2005 6,643,187'Compressed event counting technique and application to a flash memory system'2003 6,345,001'Compressed event counting technique and application to a flash memory system'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2012Patents assigned to SANDISK CORP (120)· patent assignee history

2002–2019Based in Los Gatos, CA, US· patent location history

2011–2018Patents assigned to SANDISK TECHNOLOGIES INC (41)· patent assignee history

2012–2014Patents assigned to MOKHLESI NIMA (28)· patent assignee history

2012–2013Patents assigned to CHIN HENRY (7)· patent assignee history

2015–2018Based in Los Altos, CA, US· patent location history

2017–2019Patents assigned to SANDISK TECHNOLOGIES LLC (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SANDISK CORP	120	2002–2012
SANDISK TECHNOLOGIES INC	41	2011–2018
MOKHLESI NIMAself	28	2012–2014
SANDISK TECHNOLOGIES LLC	10	2017–2019
CHIN HENRY	7	2012–2013

Locations

Location	Patents	Span
Los Gatos, California, US	177	2002–2019
Los Altos, California, US	4	2015–2018