Inventor

David B. Scott

Inventor

Plano, TX, US

Overview

55→

Patents

1983–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 55 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices26%

G11CStatic stores18%

H03KPulse technique10%

G06FElectric digital data processing8%

H10BElectronic memory devices7%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

G01RMeasuring electric variables3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%

PatentTitleYear

10,872,190Method and system for latch-up prevention2020 9,385,213'Integrated circuits and manufacturing methods thereof'2016 8,804,450'Memory circuits having a diode-connected transistor with back-biased control'2014 8,504,972'Standard cells having flexible layout architecture/boundaries'2013 8,432,071'Method and apparatus for energy harvest from ambient sources'2013 8,411,525'Memory circuits having a diode-connected transistor with back-biased control'2013 8,362,573'Integrated circuits and manufacturing methods thereof'2013 8,122,406'Generating models for integrated circuits with sensitivity-based minimum change to existing models'2012 7,639,056'Ultra low area overhead retention flip-flop for power-down applications'2009 7,519,925'Integrated circuit with dynamically controlled voltage supply'2009 7,466,578'Methods and systems for read-only memory'2008 7,407,850'N+ poly on high-k dielectric for semiconductor devices'2008 7,376,038'Fast access memory architecture'2008 7,307,471'Adaptive voltage control and body bias for performance and energy optimization'2007 7,282,905'System and method for IDDQ measurement in system on a chip (SOC) design'2007 7,236,396'Area efficient implementation of small blocks in an SRAM array'2007 7,216,310'Design method and system for optimum performance in integrated circuits that use power management'2007 7,180,208'Switch structure for reduced voltage fluctuation in power domains and sub-domains'2007 7,164,291'Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors'2007 7,162,652'Integrated circuit dynamic parameter management in response to dynamic energy evaluation'2007 7,091,766'Retention register for system-transparent state retention'2006 6,989,702'Retention register with normal functionality independent of retention power supply'2006 6,956,398'Leakage current reduction method'2005 6,831,337'Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (ESD) protection'2004 6,773,972'Memory cell with transistors having relatively high threshold voltages in response to selective gate doping'2004 6,730,582'Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (ESD) protection'2004 6,727,578'Semiconductor device having power supply voltage routed through substrate'2004 6,678,202'Reduced standby power memory array and method'2004 6,620,692'Method of forming a metal oxide semiconductor transistor with self-aligned channel implant'2003 6,426,655'Row decoder with switched power supply'2002 6,278,297'Row decoder with switched power supply'2001 6,249,452'Semiconductor device having offset twisted bit lines'2001 6,178,136'Semiconductor memory device having Y-select gate voltage that varies according to memory cell access operation'2001 6,141,259'Dynamic random access memory having reduced array voltage'2000 5,656,524'Method of forming a polysilicon resistor using an oxide, nitride stack'1997 5,552,724'Power-down reference circuit for ECL gate circuitry'1996 5,506,874'Phase detector and method'1996 5,424,660'DECL logic gates which operate with a 3.3 volt supply or less'1995 5,352,924'Bipolar layout for improved performance'1994 5,291,444'Combination DRAM and SRAM memory array'1994 5,227,269'Method for fabricating high density DRAM reticles'1993 5,104,817'Method of forming bipolar transistor with integral base emitter load resistor'1992 5,102,811'High voltage bipolar transistor in BiCMOS'1992 5,079,441'Integrated circuit having an internal reference circuit to supply internal logic circuits with a reduced voltage'1992 5,070,381'High voltage lateral transistor'1991 5,021,851'NMOS source/drain doping with both P and As'1991 5,019,888'Circuit to improve electrostatic discharge protection'1991 4,984,196'High performance bipolar differential sense amplifier in a BiCMOS SRAM'1991 4,851,360'NMOS source/drain doping with both P and As'1989 4,777,147'Forming a split-level CMOS device'1988 4,754,314'Split-level CMOS'1988 4,476,482'Silicide contacts for CMOS devices'1984 4,420,344'CMOS Source/drain implant process without compensation of polysilicon doping'1983 4,406,710'Mask-saving technique for forming CMOS source/drain regions'1983 4,374,700'Method of manufacturing silicide contacts for CMOS devices'1983

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1983–2009Patents assigned to TEXAS INSTRUMENTS INC (46)· patent assignee history

1983–2013Patents assigned to SCOTT DAVID B (4)· patent assignee history

1983–2016Based in Plano, TX, US· patent location history

2007Based in Dallas, TX, US· patent location history

2012–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (7)· patent assignee history

2012–2013Patents assigned to TZENG JIANN-TYNG (2)· patent assignee history

2013Patents assigned to SCOTT DAVID BARRY (2)· patent assignee history

2020Based in Hsinchu, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TEXAS INSTRUMENTS INC	46	1983–2009
TAIWAN SEMICONDUCTOR MFG	7	2012–2016
SCOTT DAVID Bself	4	1983–2013
SCOTT DAVID BARRYself	2	2013
TZENG JIANN-TYNG	2	2012–2013

Locations

Location	Patents	Span
Plano, Texas, US	53	1983–2016
Hsinchu, TW	1	2020
Dallas, Texas, US	1	2007