Inventor
Chien-Hsiun Lee
Inventor
Hsinchu, TW
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1059%
H01LSemiconductor devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
H05KPrinted circuits4%
H10DInorganic electric semiconductor devices4%
B29CShaping or joining of plastics1%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form1%
PatentTitleYear
10,777,431Post-passivation interconnect structure and method of forming the same202010,665,565Package assembly202010,453,815Methods and apparatus for solder connections201910,192,848Package assembly201910,163,877System in package process flow20189,905,520'Solder ball protection structure with thick polymer layer'20189,780,064'Method of forming package assembly'20179,768,105'Rigid interconnect structures in package-on-package assemblies'20179,515,036'Methods and apparatus for solder connections'20169,449,941'Connecting function chips to a package to form package-on-package'20169,240,387'Wafer-level chip scale package with re-workable underfill'20169,105,552'Package on package devices and methods of packaging semiconductor dies'20159,059,109'Package assembly and method of forming the same'20158,987,605'Formation of connectors without UBM'20158,932,906'Through silicon via bonding structure'20158,823,180'Package on package devices and methods of packaging semiconductor dies'20148,743,561'Wafer-level molded structure for package assembly'20148,703,539'Multiple die packaging interposer structure and method'20148,664,039'Methods and apparatus for alignment in flip chip bonding'20148,658,464'Mold chase design for package-on-package applications'20148,652,939'Method and apparatus for die assembly'20148,597,986'System in package and method of fabricating same'20138,551,813'Wafer level IC assembly method'20138,492,263'Protected solder ball joints in wafer level chip-scale packaging'20138,426,256'Method of forming stacked-die packages'20138,334,170'Method for stacking devices'20128,247,267'Wafer level IC assembly method'20128,232,183'Process and apparatus for wafer-level flip-chip assembly'20128,174,114'Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency'20128,169,076'Interconnect structures having lead-free solder bumps'20128,039,315'Thermally enhanced wafer level package'20117,977,155'Wafer-level flip-chip assembly methods'20117,851,916'Strain silicon wafer with a crystal orientation (100) in flip chip BGA package'20107,846,769'Stratified underfill method for an IC package'20107,842,548'Fixture for P-through silicon via assembly'20107,838,424'Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching'20107,833,896'Aluminum cap for reducing scratch and wire-bond bridging of bond pads'20107,772,691'Thermally enhanced wafer level package'20107,656,042'Stratified underfill in an IC package'20107,573,138'Stress decoupling structures for flip-chip assembly'20097,491,624'Method of manufacturing low CTE substrates for use with low-k flip-chip package devices'20097,170,159'Low CTE substrates for use with low-k flip-chip package devices'20077,148,560'IC chip package structure and underfill process'20067,026,711'Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA)'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (32)· patent assignee history
2006–2019Based in Hsinchu, TW· patent location history
2010–2013Based in Hsin Chu, TW· patent location history
2012–2017Patents assigned to LEE CHIEN-HSIUN (20)· patent assignee history
2012–2017Patents assigned to LII MIRNG-JI (7)· patent assignee history
2013–2016Patents assigned to WANG TSUNG-DING (8)· patent assignee history
2014–2020Based in Chu-tung Town, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (10)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 32 | 2006–2016 |
| LEE CHIEN-HSIUNself | 20 | 2012–2017 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 10 | 2016–2020 |
| WANG TSUNG-DING | 8 | 2013–2016 |
| LII MIRNG-JI | 7 | 2012–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 27 | 2006–2019 |
| Chu-tung Town, TW | 15 | 2014–2020 |
| Hsin Chu, TW | 2 | 2010–2013 |