Inventor
Derek J. Gochnour
Inventor
Boise, ID, US
Overview
Patents· 88 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
Y10Tprimary
Y10TTechnical subjects covered by former us classification19%
G01RMeasuring electric variables18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
B28DWorking stone or stone-like materials10%
H05KPrinted circuits9%
G06FElectric digital data processing3%
H01RElectrically-conductive connections3%
H01LSemiconductor devices2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
PatentTitleYear
10,770,492Chip scale package and related methods202010,079,254Chip scale package and related methods20189,754,983'Chip scale package and related methods'20177,561,938'Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICs will undergo, such as additional repairs'20097,387,119'Dicing saw with variable indexing capability'20087,166,252'Method for reducing warpage during application and curing of encapsulant materials on a printed circuit board'20077,155,300'Method for using data regarding manufacturing procedures integrated circuits (IC\'s) have undergone, such as repairs, to select procedures the IC\'s will undergo, such as additional repairs'20067,120,513'Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs'20067,049,840'Hybrid interconnect and system for testing semiconductor dice'20067,022,533'Substrate mapping'20067,011,532'Spring element for use in an apparatus for attaching to a semiconductor and a method of making'20066,970,359'Reduced-sized memory card package, length-extending adaptor and method of forming adaptor'20056,939,145'Spring element for use in an apparatus for attaching to a semiconductor and a method of making'20056,932,077'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions and dicing apparatus'20056,897,571'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20056,888,159'Substrate mapping'20056,865,086'Apparatus and method to secure an adaptor to a reduced-sized memory card'20056,841,796'Substrate mapping'20056,830,719'Method for reducing warpage during application and curing of encapsulant materials on a printed circuit board'20046,808,947'Substrate mapping'20046,806,493'Spring element for use in an apparatus for attaching to a semiconductor and a method of attaching'20046,764,549'Method and apparatus for reducing warpage during application and curing of encapsulant materials on a printed circuit board'20046,730,999'Clip chip carrier'20046,710,612'CSP BGA test socket with insert and method'20046,703,640'Spring element for use in an apparatus for attaching to a semiconductor and a method of attaching'20046,691,696'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20046,687,990'Sawing method employing multiple indexing techniques and semiconductor device structures fabricated thereby'20046,656,754'Method of forming a semiconductor chip carrier'20036,642,730'Test carrier with molded interconnect for testing semiconductor components'20036,631,662'Apparatus for sawing wafers employing multiple indexing techniques for multiple die dimensions'20036,630,836'CSP BGA test socket with insert'20036,628,128'CSP BGA test socket with insert and method'20036,598,290'Method of making a spring element for use in an apparatus for attaching to a semiconductor'20036,592,670'Apparatus for reducing warpage during application and curing of encapsulant materials on a printed circuit board'20036,578,458'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20036,555,400'Method for substrate mapping'20036,553,276'Method of using data regarding manufacturing procedures integrated circuits (IC\'s) have undergone, such as repairs, to select procedures the IC\'s will undergo, such as additional repairs'20036,544,461'Test carrier with molded interconnect for testing semiconductor components'20036,527,999'Method for reducing warpage during application and curing of encapsulant materials on a printed circuit board'20036,493,934'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20026,459,105'Apparatus for sawing wafers employing multiple indexing techniques for multiple die dimensions'20026,456,100'Apparatus for attaching to a semiconductor'20026,441,628'CSP BGA test socket with insert and method'20026,427,676'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20026,423,616'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20026,401,580'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20026,396,291'Method for testing semiconductor components'20026,388,458'Spring element for use in an apparatus for attaching to a semiconductor and a method of making'20026,369,595'CSP BGA test socket with insert and method'20026,363,295'Method for using data regarding manufacturing procedures integrated circuits (IC\'s) have undergone, such as repairs, to select procedures the IC\'s will undergo, such as additional repairs'20026,353,326'Test carrier with molded interconnect for testing semiconductor components'20026,351,034'Clip chip carrier'20026,313,651'Carrier and system for testing bumped semiconductor components'20016,307,394'Test carrier with variable force applying mechanism for testing semiconductor components'20016,300,782'System for testing semiconductor components having flexible interconnect'20016,297,660'Test carrier with variable force applying mechanism for testing semiconductor components'20016,279,563'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20016,263,566'Flexible semiconductor interconnect fabricated by backslide thinning'20016,255,840'Semiconductor package with wire bond protective member'20016,255,196'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20016,250,192'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20016,247,629'Wire bond monitoring system for layered packages'20016,242,931'Flexible semiconductor interconnect fabricated by backside thinning'20016,232,243'Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps'20016,224,936'Method for reducing warpage during application and curing of encapsulant materials on a printed circuit board'20016,208,157'Method for testing semiconductor components'20016,196,096'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20016,180,527'Method and apparatus for thinning article, and article'20016,155,247'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20006,119,675'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20006,085,962'Wire bond monitoring system for layered packages'20006,072,326'System for testing semiconductor components'20006,057,597'Semiconductor package with pre-fabricated cover'20006,040,702'Carrier and system for testing bumped semiconductor components'20006,025,731'Hybrid interconnect and system for testing semiconductor dice'20006,025,728'Semiconductor package with wire bond protective member'20006,006,739'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'19995,962,921'Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps'19995,915,755'Method for forming an interconnect for testing unpackaged semiconductor dice'19995,907,492'Method for using data regarding manufacturing procedures integrated circuits (IC\'s) have undergone, such as repairs, to select procedures the IC\'s will undergo, such as additional repairs'19995,893,726'Semiconductor package with pre-fabricated cover and method of fabrication'19995,726,075'Method for fabricating microbump interconnect for bare semiconductor dice'19985,678,301'Method for forming an interconnect for testing unpackaged semiconductor dice'19975,653,017'Method of mechanical and electrical substrate connection'19975,537,738'Methods of mechanical and electrical substrate connection'19965,342,807'Soft bond for semiconductor dies'19945,336,649'Removable adhesives for attachment of semiconductor dies'19945,173,451'Soft bond for semiconductor dies'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2009Patents assigned to MICRON TECHNOLOGY INC (82)· patent assignee history
1992–2020Based in Boise, ID, US· patent location history
1996–1997Patents assigned to MICRON DISPLAY TECH INC (2)· patent assignee history
2017–2020Patents assigned to SEMICONDUCTOR COMPONENTS IND LLC (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 82 | 1992–2009 |
| SEMICONDUCTOR COMPONENTS IND LLC | 3 | 2017–2020 |
| MICRON DISPLAY TECH INC | 2 | 1996–1997 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 88 | 1992–2020 |