Inventor
Shidong Li
Inventor
Poughkeepsie, NY, US
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices31%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H05KPrinted circuits7%
Y10TTechnical subjects covered by former us classification4%
G06FElectric digital data processing2%
H01QAntennas, i.e. radio aerials2%
A47BTables1%
A47FSpecial furniture, fittings, or accessories for shops, storehouses, bars, restaurants or the like1%
A61KPreparations for medical, dental or toiletry purposes1%
PatentTitleYear
10,877,202Surface light source assembly and refrigerator having the same202010,804,181Heterogeneous thermal interface material for corner and or edge degradation mitigation202010,685,919Reduced-warpage laminate structure202010,636,750Step pyramid shaped structure to reduce dicing defects202010,636,746Method of forming an electronic package202010,607,928Reduction of laminate failure in integrated circuit (IC) device carrier202010,593,564Lid attach optimization to limit electronic package warpage202010,566,313Integrated circuit chip carrier with in-plane thermal conductance layer202010,460,956Interposer with lattice construction and embedded conductive metal structures201910,381,276Test cell for laminate and method201910,332,813Lid attach optimization to limit electronic package warpage201910,249,548Test cell for laminate and method201910,083,886Lid attach optimization to limit electronic package warpage201810,083,919Packaging for high speed chip to chip communication201810,056,268Limiting electronic package warpage201810,049,896Lid attach optimization to limit electronic package warpage20189,953,935Packaging for high speed chip to chip communication20189,947,603Lid attach optimization to limit electronic package warpage20189,892,935'Limiting electronic package warpage with semiconductor chip lid and lid-ring'20189,818,682'Laminate substrates having radial cut metallic planes'20179,775,794'Use of gelatin or deeply processed gelatin materials in preparation of hair quality-improving compositions'20179,673,064'Interposer with lattice construction and embedded conductive metal structures'20179,666,539'Packaging for high speed chip to chip communication'20179,613,915'Reduced-warpage laminate structure'20179,543,255'Reduced-warpage laminate structure'20179,466,538'Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process'20169,443,799'Interposer with lattice construction and embedded conductive metal structures'20169,293,439'Electronic module assembly with patterned adhesive array'20169,093,563'Electronic module assembly with patterned adhesive array'20159,089,051'Multichip module with stiffening frame and associated covers'20159,089,052'Multichip module with stiffening frame and associated covers'20158,940,550'Maintaining laminate flatness using magnetic retention during chip joining'20157,446,728'Method and apparatus for constructing general wireless antenna systems'20086,911,954'Method for constructing mobile wireless antenna systems'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008Patents assigned to LI SHIDONG (1)· patent assignee history
2008Based in Millbrae, CA, US· patent location history
2015–2020Patents assigned to IBM (28)· patent assignee history
2015–2020Based in Poughkeepsie, NY, US· patent location history
2016Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
2017Patents assigned to DONG-E E-JIAO CO LTD (1)· patent assignee history
2017Based in Liaocheng, CN· patent location history
2020Patents assigned to QINGDAO HAIER CO LTD (1)· patent assignee history
2020Based in Hopewell Junction, NY, US· patent location history
2020Based in Qingdao, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 28 | 2015–2020 |
| GLOBALFOUNDRIES INC | 2 | 2016 |
| DONG-E E-JIAO CO LTD | 1 | 2017 |
| LI SHIDONGself | 1 | 2008 |
| QINGDAO HAIER CO LTD | 1 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 28 | 2015–2020 |
| Hopewell Junction, New York, US | 2 | 2020 |
| Qingdao, CN | 1 | 2020 |
| Liaocheng, CN | 1 | 2017 |
| Millbrae, California, US | 1 | 2008 |