Inventor
Chiahsun Tseng
Inventor
Wynantskill, NY, US
Overview
Patents· 53 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices32%
H10DInorganic electric semiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
B82YSpecific uses or applications of nanostructures2%
H10BElectronic memory devices2%
Y10TTechnical subjects covered by former us classification2%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
10,566,454Self-aligned contact process enabled by low temperature202010,529,858FinFET with merge-free fins202010,217,696Non-bridging contact via structures in proximity201910,170,471Bulk fin formation with vertical fin sidewall profile201910,170,327Fin density control of multigate devices through sidewall image transfer processes201910,037,944Self-aligned contact process enabled by low temperature201810,020,303Methods for forming FinFETs having epitaxial Si S/D extensions with flat top surfaces on a SiGe seed layer20189,997,367Non-lithographic line pattern formation20189,991,255FinFETs with non-merged epitaxial S/D extensions on a seed layer and having flat top surfaces20189,991,258FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator20189,985,030FinFET semiconductor device having integrated SiGe fin20189,947,791FinFET with merge-free fins20189,941,191Non-bridging contact via structures in proximity20189,728,419'Fin density control of multigate devices through sidewall image transfer processes'20179,728,534'Densely spaced fins for semiconductor fin field effect transistors'20179,646,929'Making an efuse'20179,634,117'Self-aligned contact process enabled by low temperature'20179,634,000'Partially isolated fin-shaped field effect transistors'20179,627,263'Stop layer through ion implantation for etch stop'20179,583,585'Gate structure integration scheme for fin field effect transistors'20179,552,988'Tone inverted directed self-assembly (DSA) fin patterning'20179,543,407'Low-K spacer for RMG finFET formation'20179,515,089'Bulk fin formation with vertical fin sidewall profile'20169,508,713'Densely spaced fins for semiconductor fin field effect transistors'20169,484,440'Methods for forming FinFETs with non-merged epitaxial fin extensions'20169,396,957'Non-lithographic line pattern formation'20169,391,155'Gate structure integration scheme for fin field effect transistors'20169,385,123'STI region for small fin pitch in FinFET devices'20169,368,350'Tone inverted directed self-assembly (DSA) fin patterning'20169,330,962'Non-lithographic hole pattern formation'20169,324,830'Self-aligned contact process enabled by low temperature'20169,293,345'Sidewall image transfer with a spin-on hardmask'20169,252,243'Gate structure integration scheme for fin field effect transistors'20169,245,788'Non-bridging contact via structures in proximity'20169,099,401'Sidewall image transfer with a spin-on hardmask'20159,093,326'Electrically isolated SiGe fin formation by local oxidation'20159,076,733'Self-aligned trench over fin'20159,064,901'Fin density control of multigate devices through sidewall image transfer processes'20159,064,813'Trench patterning with block first sidewall image transfer'20159,059,019'Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer'20159,059,002'Non-merged epitaxially grown MOSFET devices'20159,054,020'Double density semiconductor fins and method of fabrication'20159,054,156'Non-lithographic hole pattern formation'20159,053,965'Partially isolated Fin-shaped field effect transistors'20159,041,094'Finfet formed over dielectric'20158,969,213'Non-lithographic line pattern formation'20158,969,189'Contact structure employing a self-aligned gate cap'20158,957,478'Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer'20158,951,850'FinFET formed over dielectric'20158,872,244'Contact structure employing a self-aligned gate cap'20148,871,649'Methods of forming trench/hole type features in a layer of material of an integrated circuit product'20148,859,384'Inductor formation with sidewall image transfer'20148,796,812'Self-aligned trench over fin'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2020Patents assigned to IBM (49)· patent assignee history
2014–2018Patents assigned to RENESAS ELECTRONICS CORP (6)· patent assignee history
2014–2020Patents assigned to GLOBALFOUNDRIES INC (5)· patent assignee history
2014–2016Patents assigned to TSENG CHIAHSUN (4)· patent assignee history
2014–2015Patents assigned to YEH CHUN-CHEN (3)· patent assignee history
2014–2020Based in Wynantskill, NY, US· patent location history
2014Based in Wynanyskill, NY, US· patent location history
2016Based in Wynantskil, NY, US· patent location history
2017Based in Armonk, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 49 | 2014–2020 |
| RENESAS ELECTRONICS CORP | 6 | 2014–2018 |
| GLOBALFOUNDRIES INC | 5 | 2014–2020 |
| TSENG CHIAHSUNself | 4 | 2014–2016 |
| YEH CHUN-CHEN | 3 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wynantskill, New York, US | 50 | 2014–2020 |
| Armonk, New York, US | 1 | 2017 |
| Wynantskil, New York, US | 1 | 2016 |
| Wynanyskill, New York, US | 1 | 2014 |