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Inventor

Takao Akaogi

Inventor
Cupertino, CA, US

Overview

93→
Patents
1988–2021
Patent span
Physics
Primary field (CPC G)

Patents· 93 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores69%
H10BElectronic memory devices8%
G06FElectric digital data processing7%
G05FSystems for regulating electric or magnetic variables5%
H03KPulse technique5%
H03FAmplifiers2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
H01LSemiconductor devices1%
H10DInorganic electric semiconductor devices1%
PatentTitleYear
11,119,854Method of controlling verification operations for error correction of non-volatile memory device, and non-volatile memory device202110,297,607Non-volatile memory having discrete isolation structure and SONOS memory cell, method of operating the same, and method of manufacturing the same20199,514,824'Partial local self boosting for NAND'20168,923,083'Method of identifying damaged bitline address in non-volatile'20148,654,591'Local word line driver and flash memory array device thereof'20148,638,609'Partial local self boosting for NAND'20147,986,579'Memory device and method thereof'20117,848,146'Partial local self-boosting of a memory cell channel'20107,791,947'Non-volatile memory device and methods of using'20107,498,849'Sense amplifiers with high voltage swing'20097,312,641'Sense amplifiers with high voltage swing'20077,295,475'Flash memory programming using an indication bit to interpret state'20077,283,398'Method for minimizing false detection of states in flash memory devices'20077,260,019'Memory array'20077,260,014'Voltage supply circuit for memory array programming'20077,227,768'Power interconnect structure for balanced bitline capacitance in a memory array'20077,221,595'Semiconductor device and method of generating sense signal'20077,126,862'Decoder for memory device'20066,701,423'High speed address sequencer'20046,646,950'High speed decoder for flash memory'20036,621,761'Burst architecture for a flash memory'20036,618,288'Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics'20036,611,473'Power-saving modes for memories'20036,611,464'Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics'20036,587,395'System to set burst mode in a device'20036,566,938'System for a constant current source'20036,563,738'Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics'20036,550,028'Array VT mode implementation for a simultaneous operation flash memory device'20036,542,415'Kickb signal generator'20036,507,527'Memory line discharge before sensing'20036,487,060'Oxide protection for a booster circuit'20026,463,003'Power saving scheme for burst mode implementation during reading of data from a memory device'20026,414,874'Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics'20026,400,638'Wordline driver for flash memory read mode'20026,400,633'Power-saving modes for memories'20026,359,808'Low voltage read cascode for 2V/3V and different bank combinations without metal options for a simultaneous operation flash memory device'20026,353,566'System and method for tracking sensing speed by an equalization pulse for a high density flash memory device'20026,351,420'Voltage boost level clamping circuit for a flash memory'20026,347,052'Word line decoding architecture in a flash memory'20026,327,181'Reference cell bitline path architecture for a simultaneous operation flash memory device'20016,307,787'Burst read incorporating output based redundancy'20016,259,633'Sense amplifier architecture for sliding banks for a simultaneous operation flash memory device'20016,246,609'Decoder circuit'20016,243,316'Voltage boost reset circuit for a flash memory'20016,240,044'High speed address sequencer'20016,240,040'Multiple bank simultaneous operation for a flash memory'20016,229,735'Burst read mode word line boosting'20016,212,108'Distributed voltage charge circuits to reduce sensing time in a memory device'20016,208,556'Address transition detect timing architecture for a simultaneous operation flash memory device'20016,205,084'Burst mode flash memory'20016,201,753'Latching CAM data in a flash memory device'20016,185,128'Reference cell four-way switch for a simultaneous operation flash memory device'20016,134,146'Wordline driver for flash electrically erasable programmable read-only memory (EEPROM)'20006,125,058'System for optimizing the equalization pulse of a read sense amplifier for a simultaneous operation flash memory device'20006,118,698'Output multiplexing implementation for a simultaneous operation flash memory device'20006,111,787'Address transistion detect timing architecture for a simultaneous operation flash memory device'20006,104,667'Clock control circuit for generating an internal clock signal with one or more external clock cycles being blocked out and a synchronous flash memory device using the same'20006,014,329'Flash-erasable semiconductor memory device having an improved reliability'20005,910,916'Flash-erasable semiconductor memory device having improved reliability'19995,870,337'Flash-erasable semiconductor memory device having an improved reliability'19995,867,430'Bank architecture for a non-volatile memory enabling simultaneous reading and writing'19995,835,416'Flash-erasable semiconductor memory device having an improved reliability'19985,835,408'Flash-erasable semiconductor memory device having an improved reliability'19985,815,440'Semiconductor memory device with electrically controllable threshold voltage'19985,770,963'Flash memory with improved erasability and its circuitry'19985,761,127'Flash-erasable semiconductor memory device having an improved reliability'19985,701,274'Semiconductor device with selectable device information'19975,666,314'Semiconductor memory device for selecting and deselecting blocks of word lines'19975,640,123'Substrate voltage control circuit for a flash memory'19975,631,597'Negative voltage circuit for a flash memory'19975,608,670'Flash memory with improved erasability and its circuitry'19975,592,419'Flash memory with improved erasability and its circuitry'19975,590,074'Nonvolatile semiconductor memory'19965,576,637'XOR CMOS logic gate'19965,572,463'Nonvolatile semiconductor memory with pre-read means'19965,537,356'Nonvolatile semiconductor memory'19965,521,866'Non-volatile semiconductor memory device having floating gate'19965,519,652'Nonvolatile semiconductor memory for positively holding stored data'19965,490,107'Nonvolatile semiconductor memory'19965,487,036'Nonvolatile semiconductor memory'19965,452,251'Semiconductor memory device for selecting and deselecting blocks of word lines'19955,428,580'Nonvolatile semiconductor memory having an address-transition-detection circuit'19955,402,383'Electrically erasable non-volatile semiconductor memory device for selective use in boot block type or normal type flash memory devices'19955,309,400'Sense circuit for non-volatile memory device'19945,293,344'Write circuit for non-volatile memory device'19945,280,451'Signature circuit for non-volatile memory device'19945,237,530'Frasable non-volatile semiconductor memory device having read/write test function'19935,197,030'Semiconductor memory device having redundant memory cells'19935,091,888'Semiconductor memory device'19925,038,327'Decoder circuit of erasable programmable read only memory for avoiding erroneous operation caused by parasitic capacitors'19914,998,223'Programmable semiconductor memory apparatus'19914,802,127'Output buffer circuit for a semiconductor memory device'19894,773,046'Semiconductor device having fuse circuit and detecting circuit for detecting states of fuses in the fuse circuit'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–2004Patents assigned to FUJITSU LTD (74)· patent assignee history
1988–2003Based in Kawasaki, JP· patent location history
1991–1994Based in Inagi, JP· patent location history
1992Based in Tokyo, JP· patent location history
1996–2000Patents assigned to FUJITSU VLSI LTD (7)· patent assignee history
1999–2003Patents assigned to ADVANCED MICRO DEVICES INC (26)· patent assignee history
1999–2019Based in Cupertino, CA, US· patent location history
2006–2014Patents assigned to SPANSION LLC (13)· patent assignee history
2014–2019Patents assigned to AKAOGI TAKAO (4)· patent assignee history
2021Based in Hsinchu, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FUJITSU LTD741988–2004
ADVANCED MICRO DEVICES INC261999–2003
SPANSION LLC132006–2014
FUJITSU VLSI LTD71996–2000
AKAOGI TAKAOself42014–2019
Locations
LocationPatentsSpan
Cupertino, California, US531999–2019
Kawasaki, JP321988–2003
Inagi, JP61991–1994
Hsinchu, TW12021
Tokyo, JP11992