Inventor
Jayanta Bhadra
Inventor
Austin, TX, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing60%
G01RMeasuring electric variables8%
G06NComputing arrangements based on specific computational models8%
G11CStatic stores8%
A61KPreparations for medical, dental or toiletry purposes4%
C07DHeterocyclic compounds4%
C12NMicroorganisms or enzymes4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
PatentTitleYear
11,017,077Run-time security protection system and method202110,919,857Oligo-guanidines based cellular transporter comprising heterocyclic rings with hydrophobic and/or lipophilic groups at N-terminal for effective delivery of nonpenetrable cargos in-vitro and in-vivo202110,495,691System architecture method and apparatus for adaptive hardware fault detection with hardware metrics subsystem201910,481,674Autonomous hardware for application power usage optimization20199,824,243'Model-based runtime detection of insecure behavior for system on chip with security requirements'20179,092,567'Systems and methods for analyzing transactions in a computer system'20159,069,762'Equivalence classes over parameter state space'20159,002,694'Verification of design derived from power intent'20158,584,063'Assertion-based design partitioning'20138,555,226'Automatic verification of dependency'20138,234,618'Trace reconstruction for silicon validation of asynchronous systems-on-chip'20128,050,904'System and method for circuit symbolic timing analysis of circuit designs'20117,945,418'Stream based stimulus definition and delivery via interworking'20117,650,579'Model correspondence method and device'20107,360,183'Design analysis tool and method for deriving correspondence between storage elements of two memory models'20086,952,812'Design analysis tool for path extraction and false path identification and method thereof'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2017Patents assigned to FREESCALE SEMICONDUCTOR INC (12)· patent assignee history
2005–2021Based in Austin, TX, US· patent location history
2012–2015Patents assigned to BHADRA JAYANTA (6)· patent assignee history
2012Patents assigned to BOSE MRINAL (1)· patent assignee history
2013–2015Patents assigned to FENG XIUSHAN (4)· patent assignee history
2017–2021Patents assigned to NXP USA INC (4)· patent assignee history
2021Based in Kolkata, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FREESCALE SEMICONDUCTOR INC | 12 | 2005–2017 |
| BHADRA JAYANTAself | 6 | 2012–2015 |
| FENG XIUSHAN | 4 | 2013–2015 |
| NXP USA INC | 4 | 2017–2021 |
| BOSE MRINAL | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 15 | 2005–2021 |
| Kolkata, IN | 1 | 2021 |