LexDanaLexDanabeta
Inventor

Thungoc M. Tran

Inventor
San Jose, CA, US

Overview

61→
Patents
2002–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 61 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique35%
H04LTransmission of digital information, e.g. telegraphic communication29%
G06FElectric digital data processing8%
H03MCoding8%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses5%
G11CStatic stores4%
H04BTransmission4%
H04JMultiplex communication2%
G05FSystems for regulating electric or magnetic variables1%
H03DDemodulation or transference of modulation from one carrier to another1%
PatentTitleYear
9,405,865'Simulation tool for high-speed communications links'20169,383,763'Multimode current mirror circuitry'20169,094,239'Apparatus and method for polarity tap control'20159,077,330'Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits'20159,030,244'Clock duty cycle calibration circuitry'20158,976,804'Power supply filtering for programmable logic device having heterogeneous serial interface architecture'20158,860,482'Techniques for adjusting gears of an oscillator'20148,837,571'Apparatus and methods for on-die instrumentation'20148,705,602'Equalizer circuitry with selectable tap positions and coefficients'20148,626,474'Simulation tool for high-speed communications links'20148,619,931'Multi-purpose phase-locked loop for low cost transceiver'20138,570,197'Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits'20138,571,059'Apparatus and methods for serial interfaces with shared datapaths'20138,464,088'Multiple channel bonding in a high speed clock network'20138,416,898'Techniques for decision feedback equalization that reduce variations in the tap weight'20138,417,752'Offset cancellation in equalizer circuitry'20138,406,258'Apparatus and methods for low-jitter transceiver clocking'20138,391,350'Adaptation circuitry and methods for decision feedback equalizers'20138,290,750'Signal detect for high-speed serial interface'20128,228,102'Phase-locked loop architecture and clock distribution system'20128,208,523'Digital adaptation circuitry and methods for programmable logic devices'20128,127,215'Signal loss detector for high-speed serial interface of a programmable logic device'20128,126,079'High-speed serial data signal interface circuitry with multi-data-rate switching capability'20128,081,723'Serial data signal eye width estimator methods and apparatus'20117,996,749'Signal loss detector for high-speed serial interface of a programmable logic device'20117,944,235'High-speed serial interface circuitry for programmable logic device integrated circuits'20117,920,621'Digital adaptation circuitry and methods for programmable logic devices'20117,903,679'Power supply filtering for programmable logic device having heterogeneous serial interface architecture'20117,899,649'Signal detect for high-speed serial interface'20117,863,941'Techniques for canceling offsets in differential circuits'20117,860,203'High-speed serial data signal interface architectures for programmable logic devices'20107,855,576'Versatile common-mode driver methods and apparatus'20107,848,318'Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits'20107,812,634'Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together'20107,812,659'Clock signal circuitry for multi-channel data signaling'20107,791,370'Clock distribution techniques for channels'20107,782,935'Half-rate DFE with duplicate path for high data-rate operation'20107,777,529'Leakage compensation in dynamic flip-flop'20107,777,526'Increased sensitivity and reduced offset variation in high data rate HSSI receiver'20107,759,972'Integrated circuit architectures with heterogeneous high-speed serial interface circuitry'20107,750,674'Low-power transceiver architectures for programmable logic integrated circuit devices'20107,702,011'High-speed serial data receiver architecture'20107,697,600'Programmable receiver equalization circuitry and methods'20107,688,106'High-speed serial interface circuitry for programmable logic device integrated circuits'20107,659,745'Variable external interface circuitry on programmable logic device integrated circuits'20107,659,838'Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits'20107,656,187'Multi-channel communication circuitry for programmable logic device integrated circuits and the like'20107,586,983'Systems and methods for offset cancellation in integrated transceivers'20097,576,570'Signal amplitude detection circuitry without pattern dependencies for high-speed serial links'20097,557,615'High-speed serial data transmitter architecture'20097,482,841'Differential bang-bang phase detector (BBPD) with latency reduction'20097,460,040'High-speed serial interface architecture for a programmable logic device'20087,417,462'Variable external interface circuitry on programmable logic device integrated circuits'20087,414,429'Integration of high-speed serial interface circuitry into programmable logic device architectures'20087,403,035'Low-power transceiver architectures for programmable logic integrated circuit devices'20087,355,449'High-speed serial data transmitter architecture'20087,304,507'Modular buffering circuitry for multi-channel transceiver clock and other signals'20077,276,936'Clock circuitry for programmable logic devices'20077,245,240'Integrated circuit serializers with two-phase global master clocks'20076,556,502'Memory circuitry for programmable logic integrated circuit devices'20036,400,635'Memory circuitry for programmable logic integrated circuit devices'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2016Patents assigned to ALTERA CORP (61)· patent assignee history
2002–2016Based in San Jose, CA, US· patent location history
2011–2015Patents assigned to TRAN THUNGOC M (16)· patent assignee history
2011–2015Patents assigned to SHUMARAYEV SERGEY (14)· patent assignee history
2011–2014Patents assigned to DING WEIQI (7)· patent assignee history
2012–2015Patents assigned to HOANG TIM TRI (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALTERA CORP612002–2016
TRAN THUNGOC Mself162011–2015
SHUMARAYEV SERGEY142011–2015
HOANG TIM TRI102012–2015
DING WEIQI72011–2014
Locations
LocationPatentsSpan
San Jose, California, US612002–2016