Inventor
Chia-Chi Chung
Inventor
Hsinchu, TW
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
G03BApparatus or arrangements for taking photographs or for projecting or viewing them9%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices9%
H01LSemiconductor devices9%
H10HInorganic light-emitting semiconductor devices having potential barriers9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10BElectronic memory devices6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
B08BCleaning in general3%
B25FCombination or multi-purpose tools not otherwise provided for3%
PatentTitleYear
10,739,682Edge-exposure tool with an ultraviolet (UV) light emitting diode (LED)202010,509,323Edge-exposure tool with an ultraviolet (UV) light emitting diode (LED)201910,295,909Edge-exposure tool with an ultraviolet (UV) light emitting diode (LED)201910,155,305Multi-function multi-angle cleaning tool201810,131,539Method for forming micro-electro-mechanical system (MEMS) device structure20189,720,312'Projection screen and manufacturing method of projection screen'20178,673,788'Method of forming a layer on a semiconductor substrate having a plurality of trenches'20148,523,396'Device housing'20138,124,537'Method for etching integrated circuit structure'20127,993,018'Projection optical system and light amount adjusting component used in the same'20117,026,682'Non-volatile memory device with enlarged trapping layer'20066,790,772'Dual damascene processing method using silicon rich oxide layer thereof and its structure'20046,791,190'Self-aligned contact/borderless contact opening and method for forming same'20046,774,051'Method for reducing pitch'20046,713,332'Non-volatile memory device with enlarged trapping layer'20046,670,275'Method of rounding a topcorner of trench'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2006Patents assigned to MACRONIX INT CO LTD (6)· patent assignee history
2003–2020Based in Hsinchu, TW· patent location history
2011–2017Patents assigned to CORETRONIC CORP (3)· patent assignee history
2012–2017Patents assigned to CHUNG CHIA-CHI (4)· patent assignee history
2012–2014Patents assigned to TAIWAN SEMICONDUCTOR MFG (2)· patent assignee history
2018–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MACRONIX INT CO LTD | 6 | 2003–2006 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 5 | 2018–2020 |
| CHUNG CHIA-CHIself | 4 | 2012–2017 |
| CORETRONIC CORP | 3 | 2011–2017 |
| TAIWAN SEMICONDUCTOR MFG | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 16 | 2003–2020 |