Inventor
Weimin Li
Inventor
Boise, ID, US
Overview
Patents· 99 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
C23CCoating metallic material14%
H10DInorganic electric semiconductor devices11%
H10BElectronic memory devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H01LSemiconductor devices2%
H04JMultiplex communication2%
H04LTransmission of digital information, e.g. telegraphic communication2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
10,826,557Data transmission method, transmitter, receiver, storage medium202010,815,231[1,2,4] triazolo [1,5-a] pyridine derivative and crystalline form thereof202010,651,887Multiuser communication methods and devices for code division multiple access (CDMA)202010,611,771Pyrazolo [3,4-d] pyrimidine derivative2020D0875440Gaming desk202010,484,209Data transmission method and device201910,475,575In-situ oxidized NiO as electrode surface for high k MIM device201910,326,547Multi-user code division multiple access communication method, and corresponding transmitter and receiver201910,186,570ALD processes for low leakage current and low equivalent oxide thickness BiTaO films201910,171,128Data transmission method and apparatus201910,043,658Precursors for silicon dioxide gap fill20189,979,526Methods and apparatuses for measuring CSI20189,963,898Underwater cleaning robot20189,946,048Lens barrel module and lens assembly including the same20189,637,395'Fluorine free tungsten ALD/CVD process'20179,538,477'Uplink power control method, terminal and base station'20179,443,736'Silylene compositions and methods of use thereof'20169,337,054'Precursors for silicon dioxide gap fill'20169,322,066'Predictors for cancer treatment'20168,663,735'In situ generation of RuO4 for ALD of Ru and Ru related materials'20148,574,675'Method and composition for depositing ruthenium with assistive metal species'20138,486,612'Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials'20138,367,575'High-refractivity low-dispersion optical glass'20138,330,136'High concentration nitrogen-containing germanium telluride based memory devices and processes of making'20128,093,140'Amorphous Ge/Te deposition process'20127,910,177'Sequential pulse deposition'20117,858,518'Method for forming a selective contact and local interconnect in situ'20107,855,154'Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials'20107,678,460'Intermediate semiconductor device structures using photopatternable, dielectric materials'20107,632,737'Protection in integrated circuits'20097,550,816'Filled trench isolation structure'20097,521,354'Low k interlevel dielectric layer fabrication methods'20097,494,894'Protection in integrated circuits'20097,470,635'Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry, methods of forming trench isolation in the fabrication of integrated circuitry, methods of depositing silicon dioxide-comprising layers in the fabrication of integrated circuitry, and methods of forming bit line over capacitor arrays of memory cells'20087,470,632'Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge'20087,341,957'Masking structure having multiple layers including amorphous carbon layer'20087,314,837'Chemical treatment of semiconductor substrates'20087,298,024'Transparent amorphous carbon structure in semiconductor devices'20077,279,118'Compositions of matter and barrier layer compositions'20077,273,793'Methods of filling gaps using high density plasma chemical vapor deposition'20077,259,079'Methods for filling high aspect ratio trenches in semiconductor layers'20077,253,076'Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers'20077,235,499'Semiconductor processing methods'20077,220,683'Transparent amorphous carbon structure in semiconductor devices'20077,214,618'Technique for high efficiency metalorganic chemical vapor deposition'20077,205,248'Method of eliminating residual carbon from flowable oxide fill'20077,202,183'Method of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition'20077,186,638'Passivation processes for use with metallization techniques'20077,132,201'Transparent amorphous carbon structure in semiconductor devices'20067,129,180'Masking structure having multiple layers including an amorphous carbon layer'20067,078,356'Low K interlevel dielectric layer fabrication methods'20067,067,414'Low k interlevel dielectric layer fabrication methods'20067,067,415'Low k interlevel dielectric layer fabrication methods'20067,060,637'Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials'20067,056,833'Methods of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition'20067,053,010'Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming arrays of memory cells'20067,018,469'Atomic layer deposition methods of forming silicon dioxide comprising layers'20067,008,885'Chemical treatment of semiconductor substrates'20066,982,207'Methods for filling high aspect ratio trenches in semiconductor layers'20066,951,709'Method of fabricating a semiconductor multilevel interconnect structure'20056,936,547'Gas delivery system for deposition processes, and methods of using same'20056,930,058'Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge'20056,921,710'Technique for high efficiency metalorganic chemical vapor deposition'20056,918,960'CVD of PtRh with good adhesion and morphology'20056,889,141'Method and system to flexibly calculate hydraulics and hydrology of watersheds automatically'20056,866,900'Deposition and chamber treatment methods'20056,835,995'Low dielectric constant material for integrated circuit fabrication'20046,833,576'Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers'20046,833,605'Method of making a memory cell capacitor with Ta2O5 dielectric'20046,828,683'Semiconductor devices, and semiconductor processing methods'20046,818,500'Method of making a memory cell capacitor with Ta2O5 dielectric'20046,815,819'In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications'20046,777,308'Method of improving HDP fill process'20046,756,293'Combined gate cap or digit line and spacer deposition using HDP'20046,719,919'Composition of matter'20046,676,756'Technique for high efficiency metalorganic chemical vapor deposition'20046,613,656'Sequential pulse deposition'20036,596,583'Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers'20036,589,611'Deposition and chamber treatment methods'20036,576,538'Technique for high efficiency metalorganic chemical vapor deposition'20036,573,571'Semiconductor structure including metal nitride and metal silicide layers over active area and gate stack'20036,539,341'Method and apparatus for log information management and reporting'20036,524,975'Combined gate cap or digit line and spacer deposition using HDP'20036,515,363'In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications'20036,503,822'Methods for insitu plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications'20036,489,199'Multiple step methods for forming conformal layers'20026,472,309'In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications'20026,395,647'Chemical treatment of semiconductor substrates'20026,383,951'Low dielectric constant material for integrated circuit fabrication'20026,372,643'Method for forming a selective contact and local interconnect in situ and semiconductor devices carrying the same'20026,368,988'Combined gate cap or digit line and spacer deposition using HDP'20026,326,668'Semiconductor structure including metal nitride and metal silicide'20016,323,101'Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers'20016,281,072'Multiple step methods for forming conformal layers'20016,218,288'Multiple step methods for forming conformal layers'20016,198,144'Passivation of sidewalls of a word line stack'20016,156,674'Semiconductor processing methods of forming insulative materials'20006,140,230'Methods of forming metal nitride and silicide structures'20006,136,690'In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2013Patents assigned to MICRON TECHNOLOGY INC (71)· patent assignee history
2000–2013Based in Boise, ID, US· patent location history
2006–2008Based in Shanghai, CN· patent location history
2012–2020Patents assigned to LI WEIMIN (9)· patent assignee history
2012–2014Patents assigned to ADVANCED TECH MATERIALS (4)· patent assignee history
2012–2019Based in New Milford, CT, US· patent location history
2013–2020Based in Sichuan, CN· patent location history
2016–2019Patents assigned to ENTEGRIS INC (6)· patent assignee history
2017–2020Patents assigned to ZTE CORP (7)· patent assignee history
2017–2020Based in Shenzhen, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 71 | 2000–2013 |
| LI WEIMINself | 9 | 2012–2020 |
| ZTE CORP | 7 | 2017–2020 |
| ENTEGRIS INC | 6 | 2016–2019 |
| ADVANCED TECH MATERIALS | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 64 | 2000–2013 |
| New Milford, CT, US | 10 | 2012–2019 |
| Shanghai, CN | 8 | 2006–2008 |
| Shenzhen, CN | 7 | 2017–2020 |
| Sichuan, CN | 3 | 2013–2020 |