Inventor

Lakshminarayana B. Arimilli

Inventor

Austin, TX, US

Overview

2001–2021

Patent span

Physics

Primary field (CPC G)

Patents· 129 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing88%

H04LTransmission of digital information, e.g. telegraphic communication7%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

H04JMultiplex communication1%

H04QSelecting1%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%

PatentTitleYear

11,113,204Translation invalidation in a translation cache serving an accelerator2021 11,030,110Integrated circuit and data processing system supporting address aliasing in an accelerator2021 10,846,235Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator2020 10,831,593Live partition mobility enabled hardware accelerator address translation fault resolution2020 10,761,995Integrated circuit and data processing system having a configurable cache directory for an accelerator2020 10,585,744Managed hardware accelerator address translation fault resolution utilizing a credit2020 10,572,337Live partition mobility enabled hardware accelerator address translation fault resolution2020 10,545,816Managed hardware accelerator address translation fault resolution utilizing a credit2020 10,528,418Hardware accelerator address translation fault resolution2020 10,394,711Managing lowest point of coherency (LPC) memory using a service layer adapter2019 10,346,164Memory move instruction sequence targeting an accelerator switchboard2019 10,289,479Hardware accelerator address translation fault resolution2019 10,235,215Memory lock mechanism for a multiprocessor system2019 10,216,568Live partition mobility enabled hardware accelerator address translation fault resolution2019 10,216,653Pre-transmission data reordering for a serial interface2019 10,169,247Direct memory access between an accelerator and a processor using a coherency adapter2019 10,126,952Memory move instruction sequence targeting a memory-mapped device2018 9,996,298Memory move instruction sequence enabling software control2018 9,892,061'Direct memory access between an accelerator and a processor using a coherency adapter'2018 9,778,933'Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread'2017 9,766,890'Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread'2017 9,715,470'Direct memory access between an accelerator and a processor using a coherency adapter'2017 9,684,551'Addressing for inter-thread push communication'2017 9,678,812'Addressing for inter-thread push communication'2017 9,575,825'Push instruction for pushing a message payload from a sending thread to a receiving thread'2017 9,569,293'Push instruction for pushing a message payload from a sending thread to a receiving thread'2017 9,396,021'Techniques for dynamically assigning jobs to processors in a cluster using local job tables'2016 9,384,042'Techniques for dynamically assigning jobs to processors in a cluster based on inter-thread communications'2016 9,342,387'Hardware-assisted interthread push communication'2016 9,336,145'Techniques for cache injection in a processor system based on a shared state'2016 9,286,148'Hardware-assisted interthread push communication'2016 9,268,703'Techniques for cache injection in a processor system from a remote node'2016 9,256,540'Techniques for cache injection in a processor system using a cache injection instruction'2016 9,110,885'Techniques for cache injection in a processor system'2015 8,893,126'Binding a process to a special purpose processing element having characteristics of a processor'2014 8,893,148'Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks'2014 8,756,270'Collective acceleration unit tree structure'2014 8,751,655'Collective acceleration unit tree structure'2014 8,484,307'Host fabric interface (HFI) to perform global shared memory (GSM) operations'2013 8,443,146'Techniques for cache injection in a processor system responsive to a specific instruction sequence'2013 8,429,349'Techniques for cache injection in a processor system with replacement policy position modification'2013 8,417,778'Collective acceleration unit tree flow control and retransmit'2013 8,312,464'Hardware based dynamic load balancing of message passing interface tasks by modifying tasks'2012 8,302,109'Synchronization optimized queuing system'2012 8,281,075'Processor system and methods of triggering a block move using a system bus write command initiated by user code'2012 8,275,947'Mechanism to prevent illegal access to task address space by unauthorized tasks'2012 8,255,913'Notification to task of completion of GSM operations by initiator node'2012 8,255,635'Claiming coherency ownership of a partial cache line of data'2012 8,239,879'Notification by task of completion of GSM operations at target node'2012 8,239,524'Techniques for dynamically assigning jobs to processors in a cluster based on processor workload'2012 8,234,652'Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks'2012 8,214,603'Method and apparatus for handling multiple memory requests within a multiprocessor system'2012 8,214,424'User level message broadcast mechanism in distributed computing environment'2012 8,200,910'Generating and issuing global shared memory operations via a send FIFO'2012 8,185,896'Method for data processing using a multi-tiered full-graph interconnect architecture'2012 8,146,094'Guaranteeing delivery of multi-packet GSM messages'2012 8,140,731'System for data processing using a multi-tiered full-graph interconnect architecture'2012 8,127,300'Hardware based dynamic load balancing of message passing interface tasks'2012 8,122,132'Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information'2012 8,117,401'Interconnect operation indicating acceptability of partial data delivery'2012 8,108,619'Cache management for partial cache line operations'2012 8,108,876'Modifying an operation of one or more processors executing message passing interface tasks'2012 8,108,545'Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture'2012 8,077,602'Performing dynamic request routing based on broadcast queue depths'2011 8,024,527'Partial cache line accesses based on memory access patterns'2011 8,014,387'Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture'2011 7,996,564'Remote asynchronous data mover'2011 7,958,309'Dynamic selection of a memory access size'2011 7,958,182'Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture'2011 7,958,183'Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture'2011 7,921,316'Cluster-wide system clock in a multi-tiered full-graph interconnect architecture'2011 7,904,590'Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture'2011 7,877,436'Mechanism to provide reliability through packet drop detection'2011 7,873,879'Mechanism to perform debugging of global shared memory (GSM) operations'2011 7,840,703'System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture'2010 7,827,428'System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture'2010 7,822,889'Direct/indirect transmission of information using a multi-tiered full-graph interconnect architecture'2010 7,809,970'System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture'2010 7,797,588'Mechanism to provide software guaranteed reliability for GSM operations'2010 7,793,158'Providing reliability of communication between supernodes of a multi-tiered full-graph interconnect architecture'2010 7,779,148'Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips'2010 7,769,891'System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture'2010 7,769,892'System and method for handling indirect routing of information between supernodes of a multi-tiered full-graph interconnect architecture'2010 6,633,838'Multi-state logic analyzer integral to a microprocessor'2003 6,629,212'High speed lock acquisition mechanism with time parameterized cache coherency states'2003 6,629,214'Extended cache coherency protocol with a persistent lock acquired state'2003 6,629,209'Cache coherency protocol permitting sharing of a locked data granule'2003 6,625,701'Extended cache coherency protocol with a modified store instruction lock release indicator'2003 6,581,139'Set-associative cache memory having asymmetric latency among sets'2003 6,581,115'Data processing system with configurable memory bus and scalability ports'2003 6,553,463'Method and system for high speed access to a banked cache memory'2003 6,549,989'Extended cache coherency protocol with a lock released state'2003 6,535,939'Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations'2003 6,532,521'Mechanism for high performance transfer of speculative request data between levels of cache hierarchy'2003 6,510,494'Time based mechanism for cached speculative data deallocation'2003 6,505,277'Method for just-in-time delivery of load data by intervening caches'2003 6,496,921'Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions'2002 6,473,833'Integrated cache and directory structure for multi-level caches'2002 6,467,030'Method and apparatus for forwarding data in a hierarchial cache memory architecture'2002 6,460,117'Set-associative cache memory having a mechanism for migrating a most recently used set'2002 6,460,118'Set-associative cache memory having incremental access latencies among sets'2002 6,442,653'Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data'2002 6,434,669'Method of cache management to dynamically update information-type dependent cache policies'2002 6,434,668'Method of cache management to store information in particular regions of the cache according to information-type'2002 6,425,058'Cache management mechanism to enable information-type dependent cache policies'2002 6,421,762'Cache allocation policy based on speculative request history'2002 6,421,763'Method for instruction extensions for a tightly coupled speculative request unit'2002 6,408,362'Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data'2002 6,405,290'Multiprocessor system bus protocol for O state memory-consistent data'2002 6,397,303'Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines'2002 6,393,528'Optimized cache allocation algorithm for multiple speculative requests'2002 6,385,695'Method and system for maintaining allocation information on data castout from an upper level cache'2002 6,385,702'High performance multiprocessor system with exclusive-deallocate cache state'2002 6,374,333'Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention'2002 6,370,618'Method and system for allocating lower level cache entries for data castout from an upper level cache'2002 6,360,299'Extended cache state with prefetched stream ID information'2002 6,356,982'Dynamic mechanism to upgrade o state memory-consistent cache lines'2002 6,356,980'Method and system for bypassing cache levels when casting out from an upper level cache'2002 6,349,369'Protocol for transferring modified-unsolicited state during data intervention'2002 6,349,368'High performance mechanism to support O state horizontal cache-to-cache transfers'2002 6,345,341'Method of cache management for dynamically disabling O state memory-consistent data'2002 6,345,342'Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line'2002 6,345,344'Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits'2002 6,345,343'Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state'2002 6,338,116'Method and apparatus for a data-less write operation within a cache memory hierarchy for a data processing system'2002 6,321,306'High performance multiprocessor system with modified-unsolicited cache state'2001 6,314,498'Multiprocessor system bus transaction for transferring exclusive-deallocate cache state to lower lever cache'2001 6,298,416'Method and apparatus for transmitting control signals within a hierarchial cache memory architecture for a data processing system'2001 6,282,615'Multiprocessor system bus with a data-less castout mechanism'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Patents assigned to IBM (129)· patent assignee history

2001–2021Based in Austin, TX, US· patent location history

2011–2019Patents assigned to ARIMILLI LAKSHMINARAYANA B (26)· patent assignee history

2011–2019Patents assigned to ARIMILLI RAVI K (23)· patent assignee history

2012–2014Patents assigned to RAJAMONY RAMAKRISHNAN (14)· patent assignee history

2012–2016Patents assigned to ARIMILLI LAKSHMINARAYANA BABA (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	129	2001–2021
ARIMILLI LAKSHMINARAYANA Bself	26	2011–2019
ARIMILLI RAVI K	23	2011–2019
RAJAMONY RAMAKRISHNAN	14	2012–2014
ARIMILLI LAKSHMINARAYANA BABAself	10	2012–2016

Locations

Location	Patents	Span
Austin, Texas, US	129	2001–2021