Inventor
Kamalesh K. Srivastava
Inventor
Wappingers Falls, NY, US
Overview
Patents· 36 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H05KPrinted circuits10%
Y10TTechnical subjects covered by former us classification10%
B23KSoldering or unsoldering9%
H01LSemiconductor devices8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
Y02PClimate change mitigation technologies in the production or processing of goods5%
B82YSpecific uses or applications of nanostructures2%
C22CAlloys2%
H01BCables2%
PatentTitleYear
11,094,657Multilayer pillar for reduced stress interconnect and method of making same202110,403,590Multilayer pillar for reduced stress interconnect and method of making same201910,396,051Multilayer pillar for reduced stress interconnect and method of making same20199,640,501'Multilayer pillar for reduced stress interconnect and method of making same'20179,472,520'Multilayer pillar for reduced stress interconnect and method of making same'20169,111,816'Multilayer pillar for reduced stress interconnect and method of making same'20158,910,853'Additives for grain fragmentation in Pb-free Sn-based solder'20148,493,746'Additives for grain fragmentation in Pb-free Sn-based solder'20138,314,500'Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers'20128,293,587'Multilayer pillar for reduced stress interconnect and method of making same'20128,197,612'Optimization of metallurgical properties of a solder joint'20127,952,207'Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening'20117,932,169'Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers'20117,784,669'Method and process for reducing undercooling in a lead-free tin-rich solder alloy'20107,767,575'Forming robust solder interconnect structures by reducing effects of seed layer underetching'20107,703,661'Method and process for reducing undercooling in a lead-free tin-rich solder alloy'20107,572,726'Method of forming a bond pad on an I/C chip and resulting structure'20097,473,997'Method for forming robust solder interconnect structures by reducing effects of seed layer underetching'20097,425,278'Process of etching a titanium/tungsten surface and etchant used therein'20087,144,490'Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer'20066,995,084'Method for forming robust solder interconnect structures by reducing effects of seed layer underetching'20066,995,475'I/C chip suitable for wire bonding'20066,727,589'Dual damascene flowable oxide insulation structure and metallic barrier'20046,661,100'Low impedance power distribution structure for a semiconductor chip package'20036,622,907'Sacrificial seed layer process for forming C4 solder bumps'20036,531,069'Reactive Ion Etching chamber design for flip chip interconnections'20036,479,884'Interim oxidation of silsesquioxane dielectric for dual damascene process'20026,348,736'In situ formation of protective layer on silsesquioxane dielectric for dual damascene process'20026,329,280'Interim oxidation of silsesquioxane dielectric for dual damascene process'20016,293,457'Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization'20016,221,780'Dual damascene flowable oxide insulation structure and metallic barrier'20015,800,626'Control of gas content in process liquids for improved megasonic cleaning of semiconductor wafers and microelectronics substrates'19985,251,806'Method of forming dual height solder interconnections'19935,225,711'Palladium enhanced soldering and bonding of semiconductor device contacts'19935,130,779'Solder mass having conductive encapsulating arrangement'19925,048,744'Palladium enhanced fluxless soldering and bonding of semiconductor device contacts'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2021Patents assigned to IBM (34)· patent assignee history
1991–2021Based in Wappingers Falls, NY, US· patent location history
1998Based in Wappinger Falls, NY, US· patent location history
2012–2016Patents assigned to SRIVASTAVA KAMALESH K (6)· patent assignee history
2012–2016Patents assigned to SUNDLOF BRIAN R (5)· patent assignee history
2012–2016Patents assigned to SEMKOW KRYSTYNA W (4)· patent assignee history
2012–2016Patents assigned to JADHAV VIRENDRA R (3)· patent assignee history
2016Based in Highland Falls, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 34 | 1991–2021 |
| SRIVASTAVA KAMALESH Kself | 6 | 2012–2016 |
| SUNDLOF BRIAN R | 5 | 2012–2016 |
| SEMKOW KRYSTYNA W | 4 | 2012–2016 |
| JADHAV VIRENDRA R | 3 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 34 | 1991–2021 |
| Highland Falls, New York, US | 1 | 2016 |
| Wappinger Falls, New York, US | 1 | 1998 |