Inventor
Jeanne P. Bickford
Inventor
Essex Junction, VT, US
Overview
Patents· 74 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing45%
G01RMeasuring electric variables21%
Y02PClimate change mitigation technologies in the production or processing of goods10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H01LSemiconductor devices3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
G05BControl or regulating systems in general2%
G05FSystems for regulating electric or magnetic variables2%
G11CStatic stores2%
G01KMeasuring temperature1%
PatentTitleYear
10,794,952Product performance test binning202010,295,592Pre-test power-optimized bin reassignment following selective voltage binning201910,216,870Methodology to prevent metal lines from current pulse damage201910,067,184Product performance test binning201810,013,519Performance matching in three-dimensional (3D) integrated circuit (IC) using back-bias compensation20189,940,430Burn-in power performance optimization20189,865,486'Timing/power risk optimized selective voltage binning using non-linear voltage slope'20189,852,259Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks20179,791,502'On-chip usable life depletion meter and associated method'20179,772,374'Selective voltage binning leakage screen'20179,767,240'Temperature-aware integrated circuit design methods and systems'20179,759,767'Pre-test power-optimized bin reassignment following selective voltage binning'20179,740,815'Electromigration-aware integrated circuit design methods and systems'20179,653,330'Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning'20179,639,645'Integrated circuit chip reliability using reliability-optimized failure mechanism targeting'20179,625,325'System and method for identifying operating temperatures and modifying of integrated circuits'20179,619,609'Integrated circuit chip design methods and systems using process window-aware timing analysis'20179,618,566'Systems and methods to prevent incorporation of a used integrated circuit chip into a product'20179,569,571'Method and system for timing violations in a circuit'20179,557,378'Method and structure for multi-core chip product test and selective voltage binning disposition'20179,552,447'Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling'20179,536,796'Multiple manufacturing line qualification'20179,514,999'Systems and methods for semiconductor line scribe line centering'20169,429,619'Reliability test screen optimization'20169,269,407'System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time'20169,262,569'Balancing sensitivities with respect to timing closure for integrated circuits'20169,171,125'Limiting skew between different device types to meet performance requirements of an integrated circuit'20159,157,956'Adaptive power control using timing canonicals'20159,152,168'Systems and methods for system power estimation'20159,104,834'Systems and methods for single cell product path delay analysis'20159,064,087'Semiconductor device reliability model and methodologies for use thereof'20159,058,034'Integrated circuit product yield optimization using the results of performance path testing'20158,963,620'Controlling circuit voltage and frequency based upon location-dependent temperature'20158,938,701'Method of managing electro migration in logic designs and design structure thereof'20158,904,329'Systems and methods for single cell product path delay analysis'20148,850,380'Selective voltage binning within a three-dimensional integrated chip stack'20148,843,874'Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures'20148,839,170'Power/performance optimization through temperature/voltage control'20148,839,177'Method and system allowing for semiconductor design rule optimization'20148,839,165'Power/performance optimization through continuously variable temperature-based voltage control'20148,799,836'Yield optimization for design library elements at library element level or at product level'20148,719,763'Frequency selection with selective voltage binning'20148,631,375'Via selection in integrated circuit design'20148,578,314'Circuit design with growable capacitor arrays'20138,560,990'Method of managing electro migration in logic designs and design structure thereof'20138,543,960'Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures'20138,543,966'Test path selection and test program generation for performance testing integrated circuit chips'20138,539,429'System yield optimization using the results of integrated circuit chip performance path testing'20138,490,040'Disposition of integrated circuits using performance sort ring oscillator and performance path testing'20138,421,495'Speed binning for dynamic and adaptive power control'20138,423,945'Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes'20138,418,090'Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool'20138,302,063'Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression'20128,234,594'Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same'20128,136,066'Apparatus and computer program product for semiconductor yield estimation'20128,132,129'Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool'20128,095,907'Reliability evaluation and system fail warning methods using on chip parametric monitors'20128,010,916'Test yield estimate for semiconductor products created from a library'20117,996,808'Computer readable medium, system and associated method for designing integrated circuits with loop insertions'20117,984,394'Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same'20117,960,836'Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same'20117,917,451'Methods, apparatus, and program products to optimize semiconductor product yield prediction for performance and leakage screens'20117,810,054'Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point'20107,656,182'Testing method using a scalable parametric measurement macro'20107,560,946'Method of acceptance for semiconductor devices'20097,496,874'Semiconductor yield estimation'20097,487,477'Parametric-based semiconductor design'20097,487,476'Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool'20097,477,961'Equivalent gate count yield estimation for integrated circuit devices'20097,398,485'Yield optimization in router for systematic defects'20087,386,815'Test yield estimate for semiconductor products created from a library'20087,380,233'Method of facilitating integrated circuit design using manufactured property values'20087,089,132'Method and system for providing quality control on wafers running on a manufacturing line'20067,013,441'Method for modeling integrated circuit yield'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2020Patents assigned to IBM (57)· patent assignee history
2006–2020Based in Essex Junction, VT, US· patent location history
2009Based in Essex, VT, US· patent location history
2012–2017Patents assigned to BICKFORD JEANNE P (18)· patent assignee history
2013–2015Patents assigned to HABITZ PETER A (5)· patent assignee history
2013–2017Patents assigned to IYENGAR VIKRAM (5)· patent assignee history
2015–2019Patents assigned to GLOBALFOUNDRIES INC (21)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 57 | 2006–2020 |
| GLOBALFOUNDRIES INC | 21 | 2015–2019 |
| BICKFORD JEANNE Pself | 18 | 2012–2017 |
| HABITZ PETER A | 5 | 2013–2015 |
| IYENGAR VIKRAM | 5 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 73 | 2006–2020 |
| Essex, VT, US | 1 | 2009 |