Inventor

Jane A. Yater

Inventor

Austin, TX, US

Overview

1994–2018

Patent span

Electricity

Primary field (CPC H)

Patents· 38 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices31%

H10BElectronic memory devices21%

H01LSemiconductor devices17%

B82YSpecific uses or applications of nanostructures9%

G11CStatic stores9%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%

F25BRefrigeration machines, plants or systems4%

H10NElectric solid-state devices not otherwise provided for4%

PatentTitleYear

10,026,820Split gate device with doped region and method therefor2018 9,847,397Method of forming split gate memory with improved reliability2017 9,685,339'Scalable split gate memory cell array'2017 9,397,201'Non-volatile memory (NVM) cell and a method of making'2016 9,397,176'Method of forming split gate memory with improved reliability'2016 9,331,092'Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays'2016 9,275,864'Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates'2016 9,252,246'Integrated split gate non-volatile memory cell and logic device'2016 9,219,167'Non-volatile memory (NVM) cell'2015 9,129,855'Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology'2015 9,082,650'Integrated split gate non-volatile memory cell and logic structure'2015 9,054,208'Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays'2015 9,006,093'Non-volatile memory (NVM) and high voltage transistor integration'2015 8,969,940'Method of gate strapping in split-gate memory cell with inlaid gate'2015 8,962,416'Split gate non-volatile memory cell'2015 8,901,632'Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology'2014 8,679,912'Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor'2014 8,431,471'Method for integrating a non-volatile memory (NVM)'2013 8,372,699'Method for forming a split-gate memory cell'2013 8,329,544'Method for forming a semiconductor device having nanocrystals'2012 8,329,543'Method for forming a semiconductor device having nanocrystals'2012 7,902,022'Self-aligned in-laid split gate memory and method of making'2011 7,811,886'Split-gate thin film storage NVM cell with reduced load-up/trap-up effects'2010 7,642,163'Process of forming an electronic device including discontinuous storage elements within a dielectric layer'2010 7,471,560'Electronic device including a memory array and conductive lines'2008 7,262,997'Process for operating an electronic device including a memory array and conductive lines'2007 7,256,454'Electronic device including discontinuous storage elements and a process for forming the same'2007 7,064,030'Method for forming a multi-bit non-volatile memory device'2006 6,969,883'Non-volatile memory having a reference transistor'2005 6,964,902'Method for removing nanoclusters from selected regions'2005 6,955,967'Non-volatile memory having a reference transistor and method for forming'2005 6,839,280'Variable gate bias for a reference transistor in a non-volatile memory'2005 6,791,883'Program and erase in a thin film storage non-volatile memory'2004 6,751,125'Gate voltage reduction in a memory read'2004 5,889,287'Reversible thermoelectric converter'1999 5,623,119'Reversible thermoelectric converter'1997 5,470,395'Reversible thermoelectric converter'1995 5,356,484'Reversible thermoelectric converter'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2017Patents assigned to YATER JANE A (16)· patent assignee history

1994–1999Based in Matawan, NJ, US· patent location history

2004–2018Patents assigned to FREESCALE SEMICONDUCTOR INC (33)· patent assignee history

2004–2018Based in Austin, TX, US· patent location history

2012–2017Patents assigned to KANG SUNG-TAEG (12)· patent assignee history

2015–2017Patents assigned to HONG CHEONG MIN (8)· patent assignee history

2017–2018Patents assigned to NXP USA INC (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
FREESCALE SEMICONDUCTOR INC	33	2004–2018
YATER JANE Aself	16	1994–2017
KANG SUNG-TAEG	12	2012–2017
HONG CHEONG MIN	8	2015–2017
NXP USA INC	3	2017–2018

Locations

Location	Patents	Span
Austin, Texas, US	34	2004–2018
Matawan, New Jersey, US	4	1994–1999