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Inventor

Rakesh H. Patel

Inventor
Cupertino, CA, US

Overview

152→
Patents
1994–2015
Patent span
Electricity
Primary field (CPC H)

Patents· 152 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique42%
H04LTransmission of digital information, e.g. telegraphic communication12%
G06FElectric digital data processing10%
G11CStatic stores8%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H03MCoding3%
G01RMeasuring electric variables3%
H04BTransmission3%
H04JMultiplex communication2%
PatentTitleYear
9,160,405'Self-tuning high speed transceiver for IC wireline channel'20159,111,641'Memory circuit including memory devices, a freeze circuit and a test switch'20158,863,065'Stacked die network-on-chip for FPGA'20148,835,224'Distributing power with through-silicon-vias'20148,787,352'Heterogeneous transceiver architecture for wide range programmability of programmable logic devices'20148,743,943'High-speed data reception circuitry and methods'20148,719,753'Stacked die network-on-chip for FPGA'20148,654,898'Digital equalizer for high-speed serial communications'20148,599,598'3T device based memory circuits and arrays'20138,557,636'Stacked semiconductor substrates'20138,537,954'Method and apparatus for multi-mode clock data recovery'20138,416,845'Decision feedback equalization for variable input amplitude'20138,344,496'Distributing power with through-silicon-vias'20138,294,252'Stacked semiconductor substrates'20128,194,724'Adaptive equalization methods and apparatus for programmable logic devices'20128,189,729'Wide range and dynamically reconfigurable clock data recovery architecture'20128,155,180'Adaptive equalization methods and apparatus'20128,130,044'Phase-locked loop circuitry with multiple voltage-controlled oscillators'20128,130,559'MEMS switching device and conductive bridge device based circuits'20128,120,429'Voltage-controlled oscillator methods and apparatus'20128,014,480'Zero-delay serial communications circuitry for serial interconnects'20118,000,106'Circuit distribution to multiple integrated circuits'20117,940,814'Heterogeneous transceiver architecture for wide range programmability of programmable logic devices'20117,839,167'Interconnection and input/output resources for programmable logic integrated circuit devices'20107,812,659'Clock signal circuitry for multi-channel data signaling'20107,804,892'Circuitry for providing programmable decision feedback equalization'20107,773,668'Adaptive equalization methods and apparatus for programmable logic devices'20107,733,982'Signal adjustment receiver circuitry'20107,728,674'Voltage-controlled oscillator methods and apparatus'20107,702,011'High-speed serial data receiver architecture'20107,701,252'Stacked die network-on-chip for FPGA'20107,698,482'Multiple data rates in integrated circuit device serial interface'20107,693,691'Systems and methods for simulating link performance'20107,684,532'Clock data recovery circuitry associated with programmable logic device circuitry'20107,680,232'Method and apparatus for multi-mode clock data recovery'20107,656,323'Apparatus for all-digital serializer-de-serializer and associated methods'20107,646,217'Programmable logic device with serial interconnect'20107,639,993'Power supply circuitry for data signal transceivers on integrated circuits'20097,616,657'Heterogeneous transceiver architecture for wide range programmability of programmable logic devices'20097,589,651'Flexible signal detect for programmable logic device serial interface'20097,590,207'Modular serial interface in programmable logic device'20097,590,174'Signal adjustment receiver circuitry'2009RE040894'Sample and load scheme for observability internal nodes in a PLD'20097,577,166'Programmable logic devices with multi-standard byte synchronization and channel alignment for communication'20097,557,615'High-speed serial data transmitter architecture'20097,541,857'Comparator offset cancellation assisted by PLD resources'20097,538,578'Multiple data rates in programmable logic device serial interface'20097,539,278'Programmable transceivers that are able to operate over wide frequency ranges'20097,525,340'Programmable logic device architecture for accommodating specialized circuitry'20097,492,816'Adaptive equalization methods and apparatus'20097,492,188'Interconnection and input/output resources for programmable logic integrated circuit devices'20097,474,167'Capacitance switch circuitry for digitally controlled oscillators'20097,436,210'Next generation 8B10B architecture'20087,362,833'Dynamic special character selection for use in byte alignment circuitry'20087,355,449'High-speed serial data transmitter architecture'20087,355,462'Phase lock loop and method for operating the same'20087,343,569'Apparatus and method for reset distribution'20087,333,570'Clock data recovery circuitry associated with programmable logic device circuitry'20087,317,332'Interconnection and input/output resources for programmable logic integrated circuit devices'20087,307,446'Integrated circuit output driver circuitry with programmable preemphasis'20077,304,494'Methods and apparatus to DC couple LVDS driver to CML levels'20077,304,498'Clock circuitry for programmable logic devices'20077,292,065'Enhanced passgate structures for reducing leakage current'20077,272,677'Multi-channel synchronization for programmable logic device serial interface'20077,262,635'Interconnection resources for programmable logic integrated circuit devices'20077,227,918'Clock data recovery circuitry associated with programmable logic device circuitry'20077,183,797'Next generation 8B10B architecture'20077,151,397'Voltage controlled oscillator programmable delay cells'20067,151,470'Data converter with multiple conversions for padded-protocol interface'20067,135,887'Programmable logic device multispeed I/O circuitry'20067,132,847'Programmable slew rate control for differential output'20067,131,024'Multiple transmit data rates in programmable logic device serial interface'20067,123,052'Interconnection resources for programmable logic integrated circuit devices'20067,109,743'Integrated circuit output driver circuitry with programmable preemphasis'20067,071,726'Selectable dynamic reconfiguration of programmable embedded IP'20067,046,174'Byte alignment for serial data receiver'20067,028,270'Apparatus and method for reset distribution'20066,989,689'Interconnection and input/output resources for programmable logic integrated circuit devices'20066,985,021'Circuits and techniques for conditioning differential signals'20066,970,117'Byte alignment for serial data receiver'20056,963,223'Programmable logic devices with multi-standard byte synchronization and channel alignment for communication'20056,940,302'Integrated circuit output driver circuitry with programmable preemphasis'20056,897,680'Interconnection resources for programmable logic integrated circuit devices'20056,894,533'Interconnection and input/output resources for programmable logic integrated circuit devices'20056,888,376'Multiple data rates in programmable logic device serial interface'20056,882,176'High-performance programmable logic architecture'20056,867,616'Programmable logic device serial interface having dual-use phase-locked loop circuitry'20056,842,034'Selectable dynamic reconfiguration of programmable embedded IP'20056,831,480'Programmable logic device multispeed I/O circuitry'20046,828,620'Nonvolatile memory cell with low doping region'20046,771,105'Voltage controlled oscillator programmable delay cells'20046,750,675'Programmable logic devices with multi-standard byte synchronization and channel alignment for communication'20046,727,727'Interconnection resources for programmable logic integrated circuit devices'20046,724,222'Programmable logic with lower internal voltage circuitry'20046,724,328'Byte alignment for serial data receiver'20046,614,261'Interconnection and input/output resources for programable logic integrated circuit devices'20036,604,228'Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions'20036,593,772'Embedded memory blocks for programmable logic'20036,583,646'Overvoltage-tolerant interface for integrated circuits'20036,573,138'Nonvolatile memory cell with low doping region'20036,570,404'High-performance programmable logic architecture'20036,563,343'Circuitry for a low internal voltage'20036,525,564'Interconnection resources for programmable logic integrated circuit devices'20036,515,507'Control pin for specifying integrated circuit voltage levels'20036,486,702'Embedded memory blocks for programmable logic'20026,467,017'Programmable logic device having embedded dual-port random access memory configurable as single-port memory'20026,433,585'Overvoltage-tolerant interface for integrated circuits'20026,414,518'Circuitry for a low internal voltage integrated circuit'20026,407,576'Interconnection and input/output resources for programmable logic integrated circuit devices'20026,366,120'Interconnection resources for programmable logic integrated circuit devices'20026,353,552'PLD with on-chip memory having a shadow register'20026,351,144'Programmable logic device with unified cell structure including signal interface bumps'20026,344,758'Interface for low-voltage semiconductor devices'20026,342,794'Interface for low-voltage semiconductor devices'20026,335,635'Programmable reticle stitching'20026,317,367'FPGA with on-chip multiport memory'20016,285,211'I/O buffer circuit with pin multiplexing'20016,281,704'High-performance interconnect'20016,259,588'Input/output buffer with overcurrent protection circuit'20016,252,422'Overvoltage-tolerant interface for intergrated circuits'20016,243,304'Sample and load scheme for observability internal nodes in a PLD'20016,239,615'High-performance interconnect'20016,219,284'Programmable logic device with multi-port memory'20016,184,707'Look-up table based logic element with complete permutability of the inputs to the secondary signals'20016,175,952'Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions'20016,154,059'High performance output buffer'20006,150,840'Programmable reticle stitching'20006,151,258'Programmable logic device with multi-port memory'20006,147,511'Overvoltage-tolerant interface for integrated circuits'20006,122,209'Method of margin testing programmable interconnect cell'20006,118,302'Interface for low-voltage semiconductor devices'20006,107,854'Variable speed path circuit and method'20006,034,857'Input/output buffer with overcurrent protection circuit'20006,025,737'Circuitry for a low internal voltage integrated circuit'20006,020,758'Partially reconfigurable programmable logic device'20006,020,760'I/O buffer circuit with pin multiplexing'20006,014,334'Sample and load scheme for observability of internal nodes in a PLD'20006,011,730'Programmable logic device with multi-port memory'20006,011,744'Programmable logic device with multi-port memory'20005,949,710'Programmable interconnect junction'19995,869,980'Programming programmable transistor devices using state machines'19995,870,410'Diagnostic interface system for programmable logic system development'19995,821,771'Method and apparatus for monitoring or forcing an internal node in a programmable device'19985,821,773'Look-up table based logic element with complete permutability of the inputs to the secondary signals'19985,764,079'Sample and load scheme for observability of internal nodes in a PLD'19985,650,734'Programming programmable transistor devices using state machines'19975,483,178'Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers'19965,371,422'Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements'19945,369,314'Programmable logic device with redundant circuitry'19945,350,954'Macrocell with flexible product term allocation'19945,349,255'Programmable t.sub.co circuit'19945,317,210'I/O cell for programmable logic device providing latched, unlatched, and fast inputs'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2015Patents assigned to ALTERA CORP (151)· patent assignee history
1994–1996Based in Santa Clara, CA, US· patent location history
1997–2015Based in Cupertino, CA, US· patent location history
1998–2005Patents assigned to QUICKTURN DESIGN SYSTEMS INC (12)· patent assignee history
2012–2015Patents assigned to PATEL RAKESH H (14)· patent assignee history
2012–2014Patents assigned to WONG WILSON (8)· patent assignee history
2012–2014Patents assigned to PATEL RAKESH (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALTERA CORP1511994–2015
PATEL RAKESH Hself142012–2015
QUICKTURN DESIGN SYSTEMS INC121998–2005
WONG WILSON82012–2014
PATEL RAKESHself52012–2014
Locations
LocationPatentsSpan
Cupertino, California, US1461997–2015
Santa Clara, California, US61994–1996