Inventor
Nuwan Jayasena
Inventor
Sunnyvale, CA, US
Overview
Patents· 71 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing49%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use15%
G11CStatic stores10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
G06TImage data processing or generation, in general4%
H01LSemiconductor devices4%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%
H03KPulse technique1%
H03MCoding1%
H04LTransmission of digital information, e.g. telegraphic communication1%
PatentTitleYear
11,119,923Locality-aware and sharing-aware cache coherence for collections of processors202111,099,788Near-memory data reduction202111,055,150Fast thread wake-up through early lock release202111,049,794Circuit board with phase change material202111,030,117Protecting host memory from access by untrusted accelerators202110,990,453Improving latency by performing early synchronization operations in between sets of program operations of a thread202110,984,838Interconnect architecture for three-dimensional processing systems202110,956,536Device and method for accelerating matrix multiply operations202110,956,044Memory system with region-specific memory access scheduling202110,902,087Device and method for accelerating matrix multiply operations as a sum of outer products202110,853,904Hierarchical register file at a graphics processing unit202010,817,422Data processing system with decoupled data operations202010,802,977Memory page access counts based on page refresh202010,782,918Near-memory data-dependent gather and packing202010,749,545Compressing tags in software and hardware semi-sorted caches202010,706,101Bucketized hash tables with remap entries202010,705,972Dynamic adaptation of memory page management policy202010,585,801Prefetch kernels on a graphics processing unit202010,585,826Using processor types for processing interrupts in a computing device202010,579,557Near-memory hardened compute blocks for configurable computing substrates202010,522,193Processor with host and slave operating modes stacked with memory201910,503,641Cache coherence for processing in memory201910,409,343Control system and architecture for incorporating microelectromechanical (MEM) switches in fluid-based cooling of 3D integrated circuits201910,382,410Memory operation encryption201910,310,997System and method for dynamically allocating memory to hold pending write requests201910,310,981Method and apparatus for performing memory prefetching201910,282,309Per-page control of physical address space distribution among memory modules201910,282,308Method and apparatus for reducing TLB shootdown overheads in accelerator-based systems201910,282,292Cluster-based migration in a multi-level memory hierarchy201910,268,416Method and systems of controlling memory-to-memory copy operations201910,242,420Preemptive context switching of processes on an accelerated processing device (APD) based on time quanta201910,198,369Dynamic memory remapping to reduce row-buffer conflicts201910,162,757Proactive cache coherence201810,133,672System and method for efficient pointer chasing201810,090,236Interposer having a pattern of sites for mounting chiplets201810,079,044Processor with host and slave operating modes stacked with memory201810,049,044Asynchronous cache flushing201810,042,762Light-weight cache coherence for data processors with limited data sharing201810,037,267Instruction set architecture and software support for register state migration20189,977,609Efficient accesses of data structures using processing near memory20189,947,386Thermal aware data placement and compute dispatch in a memory system20189,910,605'Page migration in a hybrid memory device'20189,875,195Data distribution among multiple managed memories20189,851,777Power gating based on cache dirtiness20179,818,455'Query operations for stacked-die memory device'20179,804,996'Computation memory operations in a logic layer of a stacked memory'20179,792,961'Distributed computing with phase change material thermal management'20179,755,964'Multi-protocol header generation system'20179,720,487'Predicting power management state duration on a per-process basis and modifying cache size based on the predicted duration'20179,535,831'Page migration in a 3D stacked hybrid memory'20179,507,632'Preemptive context switching of processes on ac accelerated processing device (APD) based on time quanta'20169,489,321'Scheduling memory accesses using an efficient row burst value'20169,471,130'Configuring idle states for entities in a computing device based on predictions of durations of idle periods'20169,442,557'Using a linear prediction to configure an idle state of an entity in a computing device'20169,344,091'Die-stacked memory device with reconfigurable logic'20169,329,893'Method for resuming an APD wavefront in which a subset of elements have faulted'20169,331,053'Stacked semiconductor chip device with phase change material'20169,299,121'Preemptive context switching'20169,286,948'Query operations for stacked-die memory device'20169,256,465'Process device context switching'20169,251,069'Mechanisms to bound the presence of cache blocks with specific properties in caches'20169,244,629'Method and system for asymmetrical processing with managed data affinity'20169,235,528'Write endurance management techniques in the logic layer of a stacked memory'20169,218,204'Processing engine for complex atomic operations'20159,213,585'Controlling sprinting for thermal capacity boosted systems'20159,135,185'Die-stacked memory device providing data translation'20159,122,522'Software mechanisms for managing task scheduling on an accelerated processing device (APD)'20158,984,255'Processing device with address translation probing and methods'20158,963,933'Method for urgency-based preemption of a process'20158,922,243'Die-stacked memory device with reconfigurable logic'20148,707,314'Scheduling compute kernel workgroups to heterogeneous processors based on historical processor execution times and utilizations'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2021Patents assigned to ADVANCED MICRO DEVICES INC (71)· patent assignee history
2014–2021Based in Sunnyvale, CA, US· patent location history
2015–2016Patents assigned to HARTOG ROBERT SCOTT (6)· patent assignee history
2015–2016Patents assigned to LEATHER MARK (6)· patent assignee history
2015–2016Patents assigned to MANTOR MICHAEL (6)· patent assignee history
2016–2017Patents assigned to JAYASENA NUWAN (6)· patent assignee history
2020–2021Based in Santa Clara, CA, US· patent location history
2020–2021Based in Cupertino, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 71 | 2014–2021 |
| HARTOG ROBERT SCOTT | 6 | 2015–2016 |
| JAYASENA NUWANself | 6 | 2016–2017 |
| LEATHER MARK | 6 | 2015–2016 |
| MANTOR MICHAEL | 6 | 2015–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 61 | 2014–2021 |
| Santa Clara, California, US | 6 | 2020–2021 |
| Cupertino, California, US | 4 | 2020–2021 |