Inventor
Larry Wissel
Inventor
Williston, VT, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing33%
G11CStatic stores26%
H03KPulse technique11%
G01RMeasuring electric variables7%
Y02PClimate change mitigation technologies in the production or processing of goods7%
H01HElectric switches4%
H04LTransmission of digital information, e.g. telegraphic communication4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
PatentTitleYear
10,691,870Checking wafer-level integrated designs for rule compliance202010,346,580Checking wafer-level integrated designs for rule compliance201910,248,755Checking wafer-level integrated designs for antenna rule compliance20199,990,459Checking wafer-level integrated designs for antenna rule compliance20189,646,125'Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor'20178,619,979'Physically unclonable function implemented through threshold voltage comparison'20137,930,663'Structure for integrated circuit for measuring set-up and hold times for a latch element'20117,826,285'Memory column redundancy scheme'20107,793,239'Method and system of modeling leakage'20107,773,437'Design structure for improved memory column redundancy scheme'20107,345,943'Unclocked eFUSE circuit'20087,315,193'Circuitry and method for programming an electrically programmable fuse'20087,098,721'Low voltage programmable eFuse with differential sensing scheme'20067,000,155'Redundancy register architecture for soft-error tolerance and methods of making the same'20066,624,677'Radiation tolerant flip-flop'20036,609,228'Latch clustering for power optimization'20036,490,708'Method of integrated circuit design by selection of noise tolerant gates'20026,426,641'Single pin performance screen ring oscillator with frequency division'20025,389,836'Branch isolation circuit for cascode voltage switch logic'19955,118,972'BiCMOS gate pull-down circuit'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2020Patents assigned to IBM (20)· patent assignee history
1992–2020Based in Williston, VT, US· patent location history
2013Patents assigned to FICKE JOEL T (1)· patent assignee history
2013Patents assigned to HALL WILLIAM E (1)· patent assignee history
2013Patents assigned to HOOK TERENCE B (1)· patent assignee history
2013Based in Essex Junction, VT, US· patent location history
2017Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 20 | 1992–2020 |
| FICKE JOEL T | 1 | 2013 |
| GLOBALFOUNDRIES INC | 1 | 2017 |
| HALL WILLIAM E | 1 | 2013 |
| HOOK TERENCE B | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Williston, VT, US | 19 | 1992–2020 |
| Essex Junction, VT, US | 1 | 2013 |