Inventor
Donald W. Brouillette
Inventor
St. Albans, VT, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1035%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H10DInorganic electric semiconductor devices12%
B23DPlaning7%
B28DWorking stone or stone-like materials7%
Y10TTechnical subjects covered by former us classification7%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems5%
H10BElectronic memory devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
B24BMachines, devices, or processes for grinding or polishing2%
PatentTitleYear
8,163,602'Ultraviolet energy curable tape and method of making a semiconductor chip using the tape'20127,902,682'Ultraviolet energy curable tape and method of making a semiconductor chip using the tape'20117,288,465'Semiconductor wafer front side protection'20077,134,933'Wafer thickness control during backside grind'20067,074,715'Use of photoresist in substrate vias during backside grind'20067,001,827'Semiconductor wafer front side protection'20066,915,795'Method and system for dicing wafers, and semiconductor structures incorporating the products thereof'20056,887,126'Wafer thickness control during backside grind'20056,888,223'Use of photoresist in substrate vias during backside grind'20056,600,213'Semiconductor structure and package including a chip having chamfered edges'20036,368,881'Wafer thickness control during backside grind'20026,328,794'Method of controlling stress in a film'20016,271,102'Method and system for dicing wafers, and semiconductor structures incorporating the products thereof'20016,171,873'Method and apparatus for preventing chip breakage during semiconductor manufacturing using wafer grinding striation information'20016,153,536'Method for mounting wafer frame at back side grinding (BSG) tool'20005,913,125'Method of controlling stress in a film'19995,888,838'Method and apparatus for preventing chip breakage during semiconductor manufacturing using wafer grinding striation information'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2012Patents assigned to IBM (17)· patent assignee history
1999–2012Based in St. Albans, VT, US· patent location history
2000Based in Georgia, VT, US· patent location history
2012Patents assigned to BROUILLETTE DONALD W (1)· patent assignee history
2012Patents assigned to KRYWANCZYK TIMOTHY C (1)· patent assignee history
2012Patents assigned to MARTEL STEVEN A (1)· patent assignee history
2012Patents assigned to WHALEN MATTHEW R (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 17 | 1999–2012 |
| BROUILLETTE DONALD Wself | 1 | 2012 |
| KRYWANCZYK TIMOTHY C | 1 | 2012 |
| MARTEL STEVEN A | 1 | 2012 |
| WHALEN MATTHEW R | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| St. Albans, VT, US | 16 | 1999–2012 |
| Georgia, VT, US | 1 | 2000 |