Inventor
Sanjeev Jahagirdar
Inventor
Folsom, CA, US
Overview
Patents· 89 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing34%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use28%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications9%
G06TImage data processing or generation, in general5%
G11CStatic stores5%
Y02PClimate change mitigation technologies in the production or processing of goods5%
G06NComputing arrangements based on specific computational models4%
Y10TTechnical subjects covered by former us classification4%
G09GArrangements or circuits for control of indicating devices using static means to present variable information2%
H02JElectric power networks1%
PatentTitleYear
11,048,605Dynamic voltage-frequency curve mangement202111,010,659Dynamic precision for neural network compute operations202110,983,581Resource load balancing based on usage and power limits202110,963,028System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time202110,955,896Power consumption management for communication bus202110,922,553Person tracking and privacy and acceleration of data using autonomous machines202110,909,652Enabling product SKUs based on chiplet configurations202110,891,707Coordination and increased utilization of graphics processors during inference202110,871,966Intelligent thread dispatch and vectorization of atomic operations202010,852,806Dual path sequential element to reduce toggles in data path202010,817,042Power savings for neural network architecture with zero activations during inference202010,803,548Disaggregation of SOC architecture202010,761,898Migrating threads between asymmetric cores in a multiple core processor202010,747,286Dynamic power budget allocation in multi-processor system202010,740,281Asymmetric performance multicore architecture with same instruction set architecture202010,691,392Regional adjustment of render rate202010,671,133Configurable power supplies for dynamic current sharing202010,558,254Power consumption management for communication bus202010,521,271Hybrid low power homogenous grapics processing units201910,490,170Adaptive multibit bus for energy optimization201910,474,458Instructions and logic to perform floating-point and integer operations for machine learning201910,459,509Dual path sequential element to reduce toggles in data path201910,430,310Dynamic voltage-frequency curve management201910,429,913Controlling power delivery to a processor via a bypass201910,409,346Controlling power delivery to a processor via a bypass201910,394,564Local closed loop efficiency control using IP metrics201910,353,706Instructions and logic to perform floating-point and integer operations for machine learning201910,346,166Intelligent thread dispatch and vectorization of atomic operations201910,303,953Person tracking and privacy and acceleration of data using autonomous machines201910,304,154Coordination and increased utilization of graphics processors during inference201910,289,179Dynamic control of liquid cooling pumps to provide thermal cooling uniformity201910,290,289Adaptive multibit bus for energy optimization201910,216,240Configurable power supplies for dynamic current sharing201910,146,283Controlling power delivery to a processor via a bypass201810,139,882System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time201810,049,080Asymmetric performance multicore architecture with same instruction set architecture20189,984,038Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor20189,874,925Method and apparatus for a zero voltage processor sleep state20189,870,044'Method and apparatus for a zero voltage processor sleep state'20189,841,807'Method and apparatus for a zero voltage processor sleep state'20179,823,719'Controlling power delivery to a processor via a bypass'20179,753,531'Method, apparatus, and system for energy efficiency and energy conservation including determining an optimal power state of the apparatus based on residency time of non-core domains in a power saving state'20179,727,388'Migrating threads between asymmetric cores in a multiple core processor'20179,696,999'Local closed loop efficiency control using IP metrics'20179,690,353'System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request'20179,588,559'Configurable power supplies for dynamic current sharing'20179,569,278'Asymmetric performance multicore architecture with same instruction set architecture'20179,563,254'System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time'20179,395,784'Independently controlling frequency of plurality of power domains in a processor system'20169,360,909'System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time'20169,280,172'Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor'20169,274,592'Technique for preserving cached information during a low power mode'20169,235,258'Method and apparatus for a zero voltage processor'20169,223,389'Method and apparatus for a zero voltage processor'20159,223,390'Method and apparatus for a zero voltage processor'20159,141,180'Method and apparatus for a zero voltage processor sleep state'20159,122,464'Method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode'20159,081,575'Method and apparatus for a zero voltage processor sleep state'20159,081,577'Independent control of processor core retention states'20158,892,861'Method and apparatus for establishing safe processor operating points'20148,874,949'Method, apparatus, and system for energy efficiency and energy conservation including enhanced temperature based voltage control'20148,850,178'Method and apparatus for establishing safe processor operating points'20148,819,461'Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply'20148,806,248'Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor'20148,769,323'Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor'20148,732,399'Technique for preserving cached information during a low power mode'20148,713,256'Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance'20148,707,066'Method and apparatus for a zero voltage processor sleep state'20148,707,062'Method and apparatus for powered off processor core mode'20148,560,871'Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor'20138,527,709'Technique for preserving cached information during a low power mode'20138,516,285'Method, apparatus and system to dynamically choose an optimum power state'20138,356,197'Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor'20138,131,989'Method and apparatus for establishing safe processor operating points'20128,122,270'Voltage stabilization for clock signal frequency locking'20128,032,772'Method, apparatus, and system for optimizing frequency and performance in a multi-die microprocessor'20118,028,181'Processor power consumption control and voltage drop via micro-architectural bandwidth throttling'20117,953,993'Method and apparatus for a zero voltage processor sleep state'20117,917,787'Method, apparatus and system to dynamically choose an aoptimum power state'20117,664,970'Method and apparatus for a zero voltage processor sleep state'20107,650,518'Method, apparatus, and system for increasing single core performance in a multi-core microprocessor'20107,516,342'Method, apparatus and system to dynamically choose an optimum power state'20097,370,189'Method and apparatus for establishing safe processor operating points in connection with a secure boot'20087,299,370'Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states'20077,290,155'Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit'20077,266,712'Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit'20077,210,054'Maintaining processor execution during frequency transitioning'20077,149,645'Method and apparatus for accurate on-die temperature measurement'20066,539,408'Preconditioning of source data for packed min/max instructions'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2021Patents assigned to INTEL CORP (89)· patent assignee history
2003Based in Orangevale, CA, US· patent location history
2006–2021Based in Folsom, CA, US· patent location history
2012–2017Patents assigned to JAHAGIRDAR SANJEEV (13)· patent assignee history
2012–2017Patents assigned to GEORGE VARGHESE (12)· patent assignee history
2012–2014Patents assigned to ALLAREY JOSE (4)· patent assignee history
2014–2017Patents assigned to JAHAGIRDAR SANJEEV S (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 89 | 2003–2021 |
| JAHAGIRDAR SANJEEVself | 13 | 2012–2017 |
| GEORGE VARGHESE | 12 | 2012–2017 |
| JAHAGIRDAR SANJEEV Sself | 5 | 2014–2017 |
| ALLAREY JOSE | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Folsom, California, US | 88 | 2006–2021 |
| Orangevale, California, US | 1 | 2003 |