Inventor
John E. Sanchez, Jr.
Inventor
Palo Alto, CA, US
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices21%
H10NElectric solid-state devices not otherwise provided for21%
G11CStatic stores20%
H01LSemiconductor devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G06FElectric digital data processing5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
B82YSpecific uses or applications of nanostructures1%
C23CCoating metallic material1%
G01BMeasuring length, thickness or similar linear dimensions1%
PatentTitleYear
11,063,214Two-terminal reversibly switchable memory device202110,833,125Memory element with a reactive metal layer202010,797,106Memory element with a reactive metal layer202010,680,171Two-terminal reversibly switchable memory device202010,340,312Memory element with a reactive metal layer201910,224,480Two-terminal reversibly switchable memory device20199,831,425Two-terminal reversibly switchable memory device20179,818,939'Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof'20179,806,130'Memory element with a reactive metal layer'20179,791,257'Determining a thickness of individual layers of a plurality of metal layers'20179,570,515'Memory element with a reactive metal layer'20179,252,359'Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof'20169,159,913'Two-terminal reversibly switchable memory device'20159,159,408'Memory element with a reactive metal layer'20158,675,389'Memory element with a reactive metal layer'20148,611,130'Method for fabricating multi-resistive state memory devices'20138,062,942'Method for fabricating multi-resistive state memory devices'20117,889,539'Multi-resistive state memory device with conductive oxide electrodes'20117,701,834'Movable terminal in a two terminal memory array'20107,633,790'Multi-resistive state memory device with conductive oxide electrodes'20097,394,679'Multi-resistive state element with reactive metal'20087,326,979'Resistive memory device with a treated interface'20087,082,052'Multi-resistive state element with reactive metal'20067,026,225'Semiconductor component and method for precluding stress-induced void formation in the semiconductor component'20066,989,604'Conformal barrier liner in an integrated circuit interconnect'20066,972,985'Memory element having islands'20056,869,878'Method of forming a selective barrier layer using a sacrificial layer'20056,836,017'Protection of low-k ILD during damascene processing with thin liner'20046,822,437'Interconnect test structure with slotted feeder lines to prevent stress-induced voids'20046,727,592'Copper interconnect with improved barrier layer'20046,723,635'Protection low-k ILD during damascene processing with thin liner'20046,657,304'Conformal barrier liner in an integrated circuit interconnect'20036,617,176'METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED'20036,525,428'Graded low-k middle-etch stop layer for dual-inlaid patterning'20035,597,458'Method for producing alloy films using cold sputter deposition process'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2006Patents assigned to ADVANCED MICRO DEVICES INC (10)· patent assignee history
1997–2021Based in Palo Alto, CA, US· patent location history
2005–2017Patents assigned to UNITY SEMICONDUCTOR CORP (15)· patent assignee history
2011–2014Patents assigned to HSIA STEVE KUO-REN (3)· patent assignee history
2011–2014Patents assigned to KINNEY WAYNE (3)· patent assignee history
2019–2021Patents assigned to HEFEI RELIANCE MEMORY LTD (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNITY SEMICONDUCTOR CORP | 15 | 2005–2017 |
| ADVANCED MICRO DEVICES INC | 10 | 1997–2006 |
| HEFEI RELIANCE MEMORY LTD | 5 | 2019–2021 |
| HSIA STEVE KUO-REN | 3 | 2011–2014 |
| KINNEY WAYNE | 3 | 2011–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 35 | 1997–2021 |