Inventor
David J. Zimmerman
Inventor
El Dorado Hills, CA, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores34%
G06FElectric digital data processing27%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use12%
G01RMeasuring electric variables5%
H01LSemiconductor devices5%
H04LTransmission of digital information, e.g. telegraphic communication4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
G01TMeasurement of nuclear or x-radiation1%
PatentTitleYear
10,795,823Dynamic partial power down of memory-side cache in a 2-level memory hierarchy202010,719,443Apparatus and method for implementing a multi-level memory hierarchy202010,541,009Write data mask for power reduction202010,504,591Adaptive configuration of non-volatile memory201910,347,354Boundary scan chain for stacked memory201910,241,912Apparatus and method for implementing a multi-level memory hierarchy201910,224,115Self-repair logic for stacked memory architecture201910,025,737Interface for storage device access over memory bus201810,026,475Adaptive configuration of non-volatile memory20189,922,725'Integrated circuit defect detection and repair'20189,646,720'Self-repair logic for stacked memory architecture'20179,600,416'Apparatus and method for implementing a multi-level memory hierarchy'20179,564,245'Integrated circuit defect detection and repair'20179,548,137'Integrated circuit defect detection and repair'20179,476,940'Boundary scan chain for stacked memory'20169,418,700'Bad block management mechanism'20169,317,429'Apparatus and method for implementing a multi-level memory hierarchy over common memory channels'20169,298,573'Built-in self-test for stacked memory architecture'20169,236,143'Generic address scrambler for memory circuit test engine'20169,195,589'Adaptive configuration of non-volatile memory'20159,190,173'Generic data scrambler for memory circuit test engine'20159,158,616'Method and system for error management in a memory device'20159,158,619'On chip redundancy repair for memory devices'20159,136,021'Self-repair logic for stacked memory architecture'20159,110,134'Input/output delay testing for devices utilizing on-chip delay generation'20159,064,560'Interface for storage device access over memory bus'20159,036,718'Low speed access to DRAM'20158,909,849'Pipeline architecture for scalable performance on memory'20148,862,973'Method and system for error management in a memory device'20148,843,794'Method, system and apparatus for evaluation of input/output buffer circuitry'20148,838,935'Apparatus, method, and system for implementing micro page tables'20148,645,777'Boundary scan chain for stacked memory'20148,619,883'Low speed access to DRAM'20138,607,089'Interface for storage device access over memory bus'20137,644,250'Defining pin functionality at device power on'20107,580,465'Low speed access to DRAM'20097,536,267'Built-in self test for memory interconnect testing'20097,533,204'Enumeration of devices on a memory channel'20097,519,891'IO self test method and apparatus for memory'20097,412,627'Method and apparatus for providing debug functionality in a buffered memory channel'20087,321,997'Memory channel self test'20087,177,211'Memory channel test fixture and method'20076,996,749'Method and apparatus for providing debug functionality in a buffered memory channel'20065,929,448'Redundant transistor dose monitor circuit using two ICs'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999Based in Sarasota, FL, US· patent location history
2006–2020Patents assigned to INTEL CORP (43)· patent assignee history
2006–2020Based in El Dorado Hills, CA, US· patent location history
2013–2020Patents assigned to ZIMMERMAN DAVID J (14)· patent assignee history
2014–2016Patents assigned to ZIMMERMAN DAVID (5)· patent assignee history
2015–2016Patents assigned to KOBLA DARSHAN (5)· patent assignee history
2015–2016Based in Folsom, CA, US· patent location history
2016–2020Patents assigned to RAMANUJAN RAJ K (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 43 | 2006–2020 |
| ZIMMERMAN DAVID Jself | 14 | 2013–2020 |
| KOBLA DARSHAN | 5 | 2015–2016 |
| ZIMMERMAN DAVIDself | 5 | 2014–2016 |
| RAMANUJAN RAJ K | 4 | 2016–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| El Dorado Hills, California, US | 41 | 2006–2020 |
| Folsom, California, US | 2 | 2015–2016 |
| Sarasota, Florida, US | 1 | 1999 |