Inventor
SCOTT WEBER
Inventor
US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H01LSemiconductor devices11%
H03KPulse technique7%
H04LTransmission of digital information, e.g. telegraphic communication7%
G06NComputing arrangements based on specific computational models5%
H05KPrinted circuits5%
A61KPreparations for medical, dental or toiletry purposes4%
C07KPeptides4%
G05FSystems for regulating electric or magnetic variables4%
PatentTitleYear
12,346,489Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA202512,347,783Interconnect architecture with silicon interposer and EMIB202512,326,749Supply voltage control systems and methods for integrated circuits202512,265,772Integrated circuit with peek and poke protection circuitry for multi-tenant usage model202512,253,870Voltage regulator circuit systems and methods202512,255,648Circuit systems and methods for reducing power supply voltage droop202512,175,288Methods and systems for processing requests using load-dependent throttling202412,076,378Use of car and bite technology coupled with an SCFV from an antibody against human thymidine kinase 1 to specifically target tumors202411,921,575Systems and methods for verifying vehicle identification number (VIN)202411,909,096Mechanically adjustable antenna positioning system202411,901,299Interconnect architecture with silicon interposer and EMIB202411,895,201Programmable integrated circuit configured as a remote trust anchor to support multitenancy202411,822,959Methods and systems for processing requests using load-dependent throttling202311,789,641Three dimensional circuit systems and methods having memory hierarchies202311,651,111Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA202311,556,677Scalable runtime validation for on-device design rule checks202311,557,541Interconnect architecture with silicon interposer and EMIB202311,489,527Three dimensional programmable logic circuit systems and methods202211,487,445Programmable integrated circuit with stacked memory die for storing configuration data202211,379,645Integrated circuit with peek and poke protection circuitry for a multi-tenant usage model202211,352,439Macrophage CAR (MOTO-CAR) in immunotherapy2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2025Patents assigned to INTEL CORP (15)· patent assignee history
2022–2024Patents assigned to ONEILL KIM LESLIE (2)· patent assignee history
2022–2024Patents assigned to WEBER SCOTT (2)· patent assignee history
2022–2025Based in US· patent location history
2023–2024Patents assigned to SHOPIFY INC (2)· patent assignee history
2023–2024Based in CA· patent location history
2025Patents assigned to ALTERA CORP (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 15 | 2022–2025 |
| ALTERA CORP | 4 | 2025 |
| ONEILL KIM LESLIE | 2 | 2022–2024 |
| SHOPIFY INC | 2 | 2023–2024 |
| WEBER SCOTTself | 2 | 2022–2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 19 | 2022–2025 |
| CA | 2 | 2023–2024 |