Inventor
THOMAS PHILIP SPEIER
Inventor
US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing84%
H04LTransmission of digital information, e.g. telegraphic communication8%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
PatentTitleYear
12,572,277Technique for managing compression of data in an apparatus202612,524,238Technique for controlling stashing of data202612,411,774Treating main memory as a collection of tagged cache lines for trace logging202512,373,350Cache-line retention hint information for conditional write instruction202512,164,441Method, apparatus, and system for storing memory encryption realm key IDs202412,093,164Efficiently replacing software breakpoint instructions in processor-based devices202412,093,186Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system202411,868,269Tracking memory block access frequency in processor-based devices202411,842,196Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions202311,803,482Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system202311,789,874Method, apparatus, and system for storing memory encryption realm key IDs202311,704,253Performing speculative address translation in processor-based devices202311,687,453Cache-based trace logging using tags in an upper-level cache202311,593,117Combining load or store instructions202311,561,896Cache-based trace logging using tags in an upper-level cache202311,550,723Method, apparatus, and system for memory bandwidth aware data prefetching202311,392,537Reach-based explicit dataflow processors, and related computer-readable media and methods202211,366,769Enabling peripheral device messaging via application portals in processor-based devices202211,232,042Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system202211,226,910Ticket based request flow control202211,188,334Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to MICROSOFT TECHNOLOGY LICENSING LLC (13)· patent assignee history
2021–2026Based in US· patent location history
2022–2024Patents assigned to QUALCOMM INC (5)· patent assignee history
2025–2026Patents assigned to ADVANCED RISC MACH LTD (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICROSOFT TECHNOLOGY LICENSING LLC | 13 | 2021–2025 |
| QUALCOMM INC | 5 | 2022–2024 |
| ADVANCED RISC MACH LTD | 3 | 2025–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 21 | 2021–2026 |