Inventor
JEREMY BINFET
Inventor
US
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing45%
G11CStatic stores42%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H01LSemiconductor devices3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
H10BElectronic memory devices2%
PatentTitleYear
12,542,170Power management across multiple packages of memory dies202612,530,135Cryptographic block locking in a non-volatile memory device202612,517,655Program command generation with dummy data generation at a memory device202612,461,667Multiple current quantization values for peak power management202512,399,630Peak power management priority override202512,393,526NAND page buffer based security operations202512,367,939Power management202512,362,022Scheduled interrupts for peak power management token ring communication202512,327,048Using duplicate data for improving error correction capability202512,237,018Memory sub-system sanitization202512,189,949Bit error management in memory devices202512,141,437Program command generation with dummy data generation at a memory device202412,119,051Memory array reset read operation202412,026,052Partitioned memory having error detection capability202412,007,912NAND page buffer based security operations202411,935,602Power management202411,915,764Apparatus and methods for thermal management in a memory202411,861,233Using duplicate data for improving error correction capability202411,830,551Memory plane access management202311,810,621Memory sub-system sanitization202311,789,629Separate partition for buffer and snapshot memory202311,776,629Threshold voltage based on program/erase cycles202311,775,208Partitions within snapshot memory for buffer and snapshot memory202311,763,895Power architecture for non-volatile memory202311,710,525Apparatus for establishing a negative body potential in a memory cell202311,694,763Read voltage calibration for copyback operation202311,670,395Peak power management self-check202311,663,104Threshold voltage distribution adjustment for buffer202311,568,933Memory plane access management202311,556,267Data management during a copyback operation202311,532,348Power management across multiple packages of memory dies202211,487,436Trims corresponding to logical unit quantity202211,481,273Partitioned memory having error detection capability202211,423,976Memory array reset read operation202211,404,129Power architecture for non-volatile memory202211,385,819Separate partition for buffer and snapshot memory202211,360,700Partitions within snapshot memory for buffer and snapshot memory202211,309,052Read voltage calibration for copyback operation202211,301,346Separate trims for buffer and snapshot202211,288,160Threshold voltage distribution adjustment for buffer2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to MICRON TECHNOLOGY INC (39)· patent assignee history
2022–2026Based in US· patent location history
2024Patents assigned to LODESTAR LICENSING GROUP LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 39 | 2022–2026 |
| LODESTAR LICENSING GROUP LLC | 1 | 2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 40 | 2022–2026 |