Inventor
Robert E. Galbraith
Inventor
Rochester, MN, US
Overview
Patents· 77 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing85%
G01RMeasuring electric variables2%
G06NComputing arrangements based on specific computational models2%
H02JElectric power networks2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B60LPropulsion of electrically-propelled vehicles1%
B60NSeats specially adapted for vehicles1%
G11BInformation storage based on relative movement between record carrier and transducer1%
G11CStatic stores1%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
PatentTitleYear
10,997,084Virtual to physical translation and media repair in storage class memory202110,990,537Logical to virtual and virtual to physical translation in storage class memory202110,942,659Persistent logical to virtual table202110,901,850Thread checkpoint table for computer processor202110,628,054Raid array systems and operations using mapping information202010,552,243Corrupt logical block addressing recovery scheme202010,528,272RAID array systems and operations using mapping information202010,467,150Dynamic tier remapping of data stored in a hybrid storage system201910,372,368Operating a RAID array with unequal stripes201910,268,589Caching data in a redundant array of independent disks (RAID) storage system201910,261,907Caching data in a redundant array of independent disks (RAID) storage system201910,078,595Implementing hardware accelerator for storage write cache management for managing cache destage rates and thresholds for storage write cache201810,067,880Dynamic tier remapping of data stored in a hybrid storage system20189,990,157Parity stripe lock engine20189,940,249Implementing hardware accelerator for storage write cache management with cache line manipulation20189,940,257Implementing hardware accelerator for storage write cache management for managing cache line updates for purges from storage write cache20189,940,254Implementing hardware accelerator for storage write cache management for simultaneous read and destage operations from storage write cache20189,940,258Implementing hardware accelerator for storage write cache management for merging data with existing data on fast writes to storage write cache20189,940,251Implementing hardware accelerator for storage write cache management for reads from storage write cache20189,940,250Implementing hardware accelerator for storage write cache management for writes to storage write cache20189,940,252Implementing hardware accelerator for storage write cache management for reads with partial read hits from storage write cache20189,940,253Implementing hardware accelerator for storage write cache management for destage operations from storage write cache20189,940,255Implementing hardware accelerator for storage write cache management for identification of data age in storage write cache20189,940,256Implementing hardware accelerator for storage write cache management for managing cache line updates for writes, reads, and destages in storage write cache20189,864,695'Implementing hardware accelerator for storage write cache management for managing cache destage rates and thresholds for storage write cache'20189,802,523'Golf cart beverage holder systems'20179,772,773'Parity stripe lock engine'20179,766,809'Parity stripe lock engine'20179,720,841'Hardware managed compressed cache'20179,690,516'Parity stripe lock engine'20179,658,968'Implementing hardware accelerator for storage write cache management'20179,582,426'Hardware managed compressed cache'20179,239,797'Implementing enhanced data caching and takeover of non-owned storage devices in dual storage device controller configuration with data in write cache'20169,213,486'Writing new data of a first block size to a second block size using a write-write mode'20159,092,364'Implementing storage adapter performance control'20159,009,490'Implementing dynamic banding of self encrypting drive'20158,886,881'Implementing storage adapter performance optimization with parity update footprint mirroring'20148,868,828'Implementing storage adapter performance optimization with cache data/directory mirroring'20148,793,462'Implementing storage adapter performance optimization with enhanced resource pool allocation'20148,667,219'Optimizing locations of data accessed by client applications interacting with a storage system'20148,661,196'Optimizing locations of data accessed by client applications interacting with a storage system'20148,656,213'Implementing storage adapter performance optimization with chained hardware operations and error recovery firmware path'20148,612,656'Implementing device physical location identification in serial attached SCSI (SAS) fabric using resource path groups'20138,544,029'Implementing storage adapter performance optimization with chained hardware operations minimizing hardware/firmware interactions'20138,516,164'Implementing storage adapter performance optimization with enhanced hardware and software interface'20138,495,258'Implementing storage adapter performance optimization with hardware accelerators offloading firmware for buffer allocation and automatically DMA'20138,495,469'Implementing enhanced IO data conversion with protection information model including parity format of data integrity fields'20138,495,259'Implementing storage adapter performance optimization with hardware chains to select performance path'20138,489,946'Managing logically bad blocks in storage devices'20138,301,942'Managing possibly logically bad blocks in storage devices'20128,196,018'Enhanced error identification with disk array parity checking'20128,195,589'Apparatus for dynamically determining primary adapter in a heterogeneous N-way adapter configuration'20127,979,655'Dynamic optimization of device limits and thresholds in a write cache'20117,925,837'Maintaining write cache and parity update footprint coherency in multiple storage adaptor configuration'20117,779,335'Enhanced error identification with disk array parity checking'20107,669,107'Method and system for increasing parallelism of disk accesses when restoring data in a disk array system'20107,493,370'Two stage method for dynamically determining primary adapter in a heterogeneous N-way adapter configuration'20097,487,394'Recovering from abnormal interruption of a parity update operation in a disk array system'20097,392,428'Method and system for recovering from abnormal interruption of a parity update operation in a disk array system'20087,392,458'Method and system for enhanced error identification with disk array parity checking'20087,290,199'Method and system for improved buffer utilization for disk array parity updates'20076,877,065'Advanced read cache management'20056,857,045'Method and system for updating data in a compressed read cache'20056,728,818'Dual storage adapters utilizing clustered adapters supporting fast write caches'20046,530,003'Method and system for maintaining data coherency in a dual input/output adapter utilizing clustered adapters'20036,338,115'Advanced read cache management'20026,286,080'Advanced read cache emulation'20016,271,647'Method and apparatus for estimating the service life of a battery'20016,191,556'Method and apparatus for estimating the service life of a battery'20016,192,450'Destage of data for write cache'20016,119,209'Backup directory for a write cache'20005,600,805'Pass-through for I/O channel subsystem call instructions for accessing shared resources in a computer system having a plurality of operating systems'19975,537,567'Parity block configuration in an array of storage devices'19965,465,355'Establishing and restoring paths in a data processing I/O system'19955,414,851'Method and means for sharing I/O resources by a plurality of operating systems'19955,265,240'Channel measurement method and means'19933,936,600'Keyboard-printer terminal interface for data processing'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976Based in Pontiac, MI, US· patent location history
1993–2021Patents assigned to IBM (74)· patent assignee history
1993–2021Based in Rochester, MN, US· patent location history
1995–1997Based in Poughkeepsie, NY, US· patent location history
2012–2014Patents assigned to GERHARD ADRIAN C (13)· patent assignee history
2012–2015Patents assigned to MOERTL DANIEL F (11)· patent assignee history
2013–2014Patents assigned to IYER MURALI N (10)· patent assignee history
2013–2014Patents assigned to BAKKE BRIAN E (9)· patent assignee history
2017Based in Pinellas Park, FL, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 74 | 1993–2021 |
| GERHARD ADRIAN C | 13 | 2012–2014 |
| MOERTL DANIEL F | 11 | 2012–2015 |
| IYER MURALI N | 10 | 2013–2014 |
| BAKKE BRIAN E | 9 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Rochester, Minnesota, US | 72 | 1993–2021 |
| Poughkeepsie, New York, US | 3 | 1995–1997 |
| Pinellas Park, Florida, US | 1 | 2017 |
| Pontiac, MI, US | 1 | 1976 |